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-rw-r--r--llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp7
-rw-r--r--llvm/lib/CodeGen/BranchFolding.cpp8
-rw-r--r--llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp9
-rw-r--r--llvm/lib/CodeGen/IfConversion.cpp54
-rw-r--r--llvm/lib/CodeGen/MachineBasicBlock.cpp2
-rw-r--r--llvm/lib/CodeGen/MachineVerifier.cpp4
-rw-r--r--llvm/lib/CodeGen/TargetInstrInfo.cpp23
-rw-r--r--llvm/lib/CodeGen/TargetSchedule.cpp2
8 files changed, 52 insertions, 57 deletions
diff --git a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
index 4483d8df27d..ed5ef30af26 100644
--- a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
+++ b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
@@ -368,7 +368,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI,
// reference either system calls or the register directly. Skip it until we
// can tell user specified registers from compiler-specified.
if (MI->isCall() || MI->hasExtraDefRegAllocReq() ||
- TII->isPredicated(MI) || MI->isInlineAsm()) {
+ TII->isPredicated(*MI) || MI->isInlineAsm()) {
DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
State->UnionGroups(Reg, 0);
}
@@ -444,9 +444,8 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI,
// instruction which may not be executed. The second R6 def may or may not
// re-define R6 so it's not safe to change it since the last R6 use cannot be
// changed.
- bool Special = MI->isCall() ||
- MI->hasExtraSrcRegAllocReq() ||
- TII->isPredicated(MI) || MI->isInlineAsm();
+ bool Special = MI->isCall() || MI->hasExtraSrcRegAllocReq() ||
+ TII->isPredicated(*MI) || MI->isInlineAsm();
// Scan the register uses for this instruction and update
// live-ranges, groups and RegRefs.
diff --git a/llvm/lib/CodeGen/BranchFolding.cpp b/llvm/lib/CodeGen/BranchFolding.cpp
index df5cac5a9f7..79eeba1bef7 100644
--- a/llvm/lib/CodeGen/BranchFolding.cpp
+++ b/llvm/lib/CodeGen/BranchFolding.cpp
@@ -167,7 +167,7 @@ bool BranchFolder::OptimizeImpDefsBlock(MachineBasicBlock *MBB) {
MachineBasicBlock::iterator FirstTerm = I;
while (I != MBB->end()) {
- if (!TII->isUnpredicatedTerminator(I))
+ if (!TII->isUnpredicatedTerminator(*I))
return false;
// See if it uses any of the implicitly defined registers.
for (const MachineOperand &MO : I->operands()) {
@@ -1623,7 +1623,7 @@ MachineBasicBlock::iterator findHoistingInsertPosAndDeps(MachineBasicBlock *MBB,
SmallSet<unsigned,4> &Uses,
SmallSet<unsigned,4> &Defs) {
MachineBasicBlock::iterator Loc = MBB->getFirstTerminator();
- if (!TII->isUnpredicatedTerminator(Loc))
+ if (!TII->isUnpredicatedTerminator(*Loc))
return MBB->end();
for (const MachineOperand &MO : Loc->operands()) {
@@ -1685,7 +1685,7 @@ MachineBasicBlock::iterator findHoistingInsertPosAndDeps(MachineBasicBlock *MBB,
// Also avoid moving code above predicated instruction since it's hard to
// reason about register liveness with predicated instruction.
bool DontMoveAcrossStore = true;
- if (!PI->isSafeToMove(nullptr, DontMoveAcrossStore) || TII->isPredicated(PI))
+ if (!PI->isSafeToMove(nullptr, DontMoveAcrossStore) || TII->isPredicated(*PI))
return MBB->end();
@@ -1765,7 +1765,7 @@ bool BranchFolder::HoistCommonCodeInSuccs(MachineBasicBlock *MBB) {
if (!TIB->isIdenticalTo(FIB, MachineInstr::CheckKillDead))
break;
- if (TII->isPredicated(TIB))
+ if (TII->isPredicated(*TIB))
// Hard to reason about register liveness with predicated instruction.
break;
diff --git a/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp b/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
index c924ba30c8a..06673ae3f30 100644
--- a/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
+++ b/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
@@ -163,9 +163,8 @@ void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr *MI) {
// instruction which may not be executed. The second R6 def may or may not
// re-define R6 so it's not safe to change it since the last R6 use cannot be
// changed.
- bool Special = MI->isCall() ||
- MI->hasExtraSrcRegAllocReq() ||
- TII->isPredicated(MI);
+ bool Special =
+ MI->isCall() || MI->hasExtraSrcRegAllocReq() || TII->isPredicated(*MI);
// Scan the register operands for this instruction and update
// Classes and RegRefs.
@@ -241,7 +240,7 @@ void CriticalAntiDepBreaker::ScanInstruction(MachineInstr *MI,
// instruction are now dead.
assert(!MI->isKill() && "Attempting to scan a kill instruction");
- if (!TII->isPredicated(MI)) {
+ if (!TII->isPredicated(*MI)) {
// Predicated defs are modeled as read + write, i.e. similar to two
// address updates.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
@@ -585,7 +584,7 @@ BreakAntiDependencies(const std::vector<SUnit>& SUnits,
// If MI's defs have a special allocation requirement, don't allow
// any def registers to be changed. Also assume all registers
// defined in a call must not be changed (ABI).
- if (MI->isCall() || MI->hasExtraDefRegAllocReq() || TII->isPredicated(MI))
+ if (MI->isCall() || MI->hasExtraDefRegAllocReq() || TII->isPredicated(*MI))
// If this instruction's defs have special allocation requirement, don't
// break this anti-dependency.
AntiDepReg = 0;
diff --git a/llvm/lib/CodeGen/IfConversion.cpp b/llvm/lib/CodeGen/IfConversion.cpp
index 41f9f0ba83d..2bf0c661629 100644
--- a/llvm/lib/CodeGen/IfConversion.cpp
+++ b/llvm/lib/CodeGen/IfConversion.cpp
@@ -668,16 +668,15 @@ void IfConverter::ScanInstructions(BBInfo &BBI) {
BBI.ExtraCost = 0;
BBI.ExtraCost2 = 0;
BBI.ClobbersPred = false;
- for (MachineBasicBlock::iterator I = BBI.BB->begin(), E = BBI.BB->end();
- I != E; ++I) {
- if (I->isDebugValue())
+ for (auto &MI : *BBI.BB) {
+ if (MI.isDebugValue())
continue;
- if (I->isNotDuplicable())
+ if (MI.isNotDuplicable())
BBI.CannotBeCopied = true;
- bool isPredicated = TII->isPredicated(I);
- bool isCondBr = BBI.IsBrAnalyzable && I->isConditionalBranch();
+ bool isPredicated = TII->isPredicated(MI);
+ bool isCondBr = BBI.IsBrAnalyzable && MI.isConditionalBranch();
// A conditional branch is not predicable, but it may be eliminated.
if (isCondBr)
@@ -685,8 +684,8 @@ void IfConverter::ScanInstructions(BBInfo &BBI) {
if (!isPredicated) {
BBI.NonPredSize++;
- unsigned ExtraPredCost = TII->getPredicationCost(&*I);
- unsigned NumCycles = SchedModel.computeInstrLatency(&*I, false);
+ unsigned ExtraPredCost = TII->getPredicationCost(MI);
+ unsigned NumCycles = SchedModel.computeInstrLatency(&MI, false);
if (NumCycles > 1)
BBI.ExtraCost += NumCycles-1;
BBI.ExtraCost2 += ExtraPredCost;
@@ -710,10 +709,10 @@ void IfConverter::ScanInstructions(BBInfo &BBI) {
// FIXME: Make use of PredDefs? e.g. ADDC, SUBC sets predicates but are
// still potentially predicable.
std::vector<MachineOperand> PredDefs;
- if (TII->DefinesPredicate(I, PredDefs))
+ if (TII->DefinesPredicate(MI, PredDefs))
BBI.ClobbersPred = true;
- if (!TII->isPredicable(I)) {
+ if (!TII->isPredicable(MI)) {
BBI.IsUnpredicable = true;
return;
}
@@ -1011,9 +1010,9 @@ void IfConverter::RemoveExtraEdges(BBInfo &BBI) {
/// Behaves like LiveRegUnits::StepForward() but also adds implicit uses to all
/// values defined in MI which are not live/used by MI.
-static void UpdatePredRedefs(MachineInstr *MI, LivePhysRegs &Redefs) {
+static void UpdatePredRedefs(MachineInstr &MI, LivePhysRegs &Redefs) {
SmallVector<std::pair<unsigned, const MachineOperand*>, 4> Clobbers;
- Redefs.stepForward(*MI, Clobbers);
+ Redefs.stepForward(MI, Clobbers);
// Now add the implicit uses for each of the clobbered values.
for (auto Reg : Clobbers) {
@@ -1491,8 +1490,8 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
if (!BBI2->BB->empty() && (DI2 == BBI2->BB->end())) {
MachineBasicBlock::iterator BBI1T = BBI1->BB->getFirstTerminator();
MachineBasicBlock::iterator BBI2T = BBI2->BB->getFirstTerminator();
- if ((BBI1T != BBI1->BB->end()) && TII->isPredicated(BBI1T) &&
- ((BBI2T != BBI2->BB->end()) && !TII->isPredicated(BBI2T)))
+ if (BBI1T != BBI1->BB->end() && TII->isPredicated(*BBI1T) &&
+ BBI2T != BBI2->BB->end() && !TII->isPredicated(*BBI2T))
--DI2;
}
@@ -1515,7 +1514,7 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
// (e.g. a predicated return). If that is the case, we cannot merge
// it with the tail block.
MachineBasicBlock::const_iterator TI = BBI.BB->getFirstTerminator();
- if (TI != BBI.BB->end() && TII->isPredicated(TI))
+ if (TI != BBI.BB->end() && TII->isPredicated(*TI))
CanMergeTail = false;
// There may still be a fall-through edge from BBI1 or BBI2 to TailBB;
// check if there are any other predecessors besides those.
@@ -1581,7 +1580,7 @@ void IfConverter::PredicateBlock(BBInfo &BBI,
bool AnyUnpred = false;
bool MaySpec = LaterRedefs != nullptr;
for (MachineBasicBlock::iterator I = BBI.BB->begin(); I != E; ++I) {
- if (I->isDebugValue() || TII->isPredicated(I))
+ if (I->isDebugValue() || TII->isPredicated(*I))
continue;
// It may be possible not to predicate an instruction if it's the 'true'
// side of a diamond and the 'false' side may re-define the instruction's
@@ -1593,7 +1592,7 @@ void IfConverter::PredicateBlock(BBInfo &BBI,
// If any instruction is predicated, then every instruction after it must
// be predicated.
MaySpec = false;
- if (!TII->PredicateInstruction(I, Cond)) {
+ if (!TII->PredicateInstruction(*I, Cond)) {
#ifndef NDEBUG
dbgs() << "Unable to predicate " << *I << "!\n";
#endif
@@ -1602,7 +1601,7 @@ void IfConverter::PredicateBlock(BBInfo &BBI,
// If the predicated instruction now redefines a register as the result of
// if-conversion, add an implicit kill.
- UpdatePredRedefs(I, Redefs);
+ UpdatePredRedefs(*I, Redefs);
}
BBI.Predicate.append(Cond.begin(), Cond.end());
@@ -1622,25 +1621,24 @@ void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
bool IgnoreBr) {
MachineFunction &MF = *ToBBI.BB->getParent();
- for (MachineBasicBlock::iterator I = FromBBI.BB->begin(),
- E = FromBBI.BB->end(); I != E; ++I) {
+ for (auto &I : *FromBBI.BB) {
// Do not copy the end of the block branches.
- if (IgnoreBr && I->isBranch())
+ if (IgnoreBr && I.isBranch())
break;
- MachineInstr *MI = MF.CloneMachineInstr(I);
+ MachineInstr *MI = MF.CloneMachineInstr(&I);
ToBBI.BB->insert(ToBBI.BB->end(), MI);
ToBBI.NonPredSize++;
- unsigned ExtraPredCost = TII->getPredicationCost(&*I);
- unsigned NumCycles = SchedModel.computeInstrLatency(&*I, false);
+ unsigned ExtraPredCost = TII->getPredicationCost(I);
+ unsigned NumCycles = SchedModel.computeInstrLatency(&I, false);
if (NumCycles > 1)
ToBBI.ExtraCost += NumCycles-1;
ToBBI.ExtraCost2 += ExtraPredCost;
if (!TII->isPredicated(I) && !MI->isDebugValue()) {
- if (!TII->PredicateInstruction(MI, Cond)) {
+ if (!TII->PredicateInstruction(*MI, Cond)) {
#ifndef NDEBUG
- dbgs() << "Unable to predicate " << *I << "!\n";
+ dbgs() << "Unable to predicate " << I << "!\n";
#endif
llvm_unreachable(nullptr);
}
@@ -1648,7 +1646,7 @@ void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
// If the predicated instruction now redefines a register as the result of
// if-conversion, add an implicit kill.
- UpdatePredRedefs(MI, Redefs);
+ UpdatePredRedefs(*MI, Redefs);
// Some kill flags may not be correct anymore.
if (!DontKill.empty())
@@ -1695,7 +1693,7 @@ void IfConverter::MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI, bool AddEdges) {
ToBBI.BB->splice(ToTI, FromBBI.BB, FromBBI.BB->begin(), FromTI);
// If FromBB has non-predicated terminator we should copy it at the end.
- if ((FromTI != FromBBI.BB->end()) && !TII->isPredicated(FromTI))
+ if (FromTI != FromBBI.BB->end() && !TII->isPredicated(*FromTI))
ToTI = ToBBI.BB->end();
ToBBI.BB->splice(ToTI, FromBBI.BB, FromTI, FromBBI.BB->end());
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
index 5cc7ba69f9c..6421b8c9d30 100644
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -691,7 +691,7 @@ bool MachineBasicBlock::canFallThrough() {
// is possible. The isPredicated check is needed because this code can be
// called during IfConversion, where an instruction which is normally a
// Barrier is predicated and thus no longer an actual control barrier.
- return empty() || !back().isBarrier() || TII->isPredicated(&back());
+ return empty() || !back().isBarrier() || TII->isPredicated(back());
}
// If there is no branch, control always falls through.
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index e1ff680354d..60f826069d1 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -630,7 +630,7 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
"differs from its CFG successor!", MBB);
}
if (!MBB->empty() && MBB->back().isBarrier() &&
- !TII->isPredicated(&MBB->back())) {
+ !TII->isPredicated(MBB->back())) {
report("MBB exits via unconditional fall-through but ends with a "
"barrier instruction!", MBB);
}
@@ -772,7 +772,7 @@ void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
// Ensure non-terminators don't follow terminators.
// Ignore predicated terminators formed by if conversion.
// FIXME: If conversion shouldn't need to violate this rule.
- if (MI->isTerminator() && !TII->isPredicated(MI)) {
+ if (MI->isTerminator() && !TII->isPredicated(*MI)) {
if (!FirstTerminator)
FirstTerminator = MI;
} else if (FirstTerminator) {
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 74b47040078..defffea1ae4 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -256,32 +256,31 @@ bool TargetInstrInfo::findCommutedOpIndices(MachineInstr *MI,
return true;
}
-bool
-TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
- if (!MI->isTerminator()) return false;
+bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
+ if (!MI.isTerminator()) return false;
// Conditional branch is a special case.
- if (MI->isBranch() && !MI->isBarrier())
+ if (MI.isBranch() && !MI.isBarrier())
return true;
- if (!MI->isPredicable())
+ if (!MI.isPredicable())
return true;
return !isPredicated(MI);
}
bool TargetInstrInfo::PredicateInstruction(
- MachineInstr *MI, ArrayRef<MachineOperand> Pred) const {
+ MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
bool MadeChange = false;
- assert(!MI->isBundle() &&
+ assert(!MI.isBundle() &&
"TargetInstrInfo::PredicateInstruction() can't handle bundles");
- const MCInstrDesc &MCID = MI->getDesc();
- if (!MI->isPredicable())
+ const MCInstrDesc &MCID = MI.getDesc();
+ if (!MI.isPredicable())
return false;
- for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ for (unsigned j = 0, i = 0, e = MI.getNumOperands(); i != e; ++i) {
if (MCID.OpInfo[i].isPredicate()) {
- MachineOperand &MO = MI->getOperand(i);
+ MachineOperand &MO = MI.getOperand(i);
if (MO.isReg()) {
MO.setReg(Pred[j].getReg());
MadeChange = true;
@@ -1035,7 +1034,7 @@ unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel &SchedModel,
return 1;
}
-unsigned TargetInstrInfo::getPredicationCost(const MachineInstr *) const {
+unsigned TargetInstrInfo::getPredicationCost(const MachineInstr &) const {
return 0;
}
diff --git a/llvm/lib/CodeGen/TargetSchedule.cpp b/llvm/lib/CodeGen/TargetSchedule.cpp
index 1c4558cea5f..f5181a362d7 100644
--- a/llvm/lib/CodeGen/TargetSchedule.cpp
+++ b/llvm/lib/CodeGen/TargetSchedule.cpp
@@ -282,7 +282,7 @@ computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
unsigned Reg = DefMI->getOperand(DefOperIdx).getReg();
const MachineFunction &MF = *DefMI->getParent()->getParent();
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
- if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(DepMI))
+ if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(*DepMI))
return computeInstrLatency(DefMI);
// If we have a per operand scheduling model, check if this def is writing
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