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-rw-r--r--llvm/lib/CodeGen/BranchRelaxation.cpp35
-rw-r--r--llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp24
-rw-r--r--llvm/lib/CodeGen/RegAllocBase.cpp11
-rw-r--r--llvm/lib/CodeGen/RegAllocBase.h32
-rw-r--r--llvm/lib/CodeGen/RegAllocFast.cpp60
-rw-r--r--llvm/lib/CodeGen/RegisterScavenging.cpp15
-rw-r--r--llvm/lib/CodeGen/SafeStack.cpp54
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp10
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAGTargetInfo.cpp5
-rw-r--r--llvm/lib/CodeGen/ShadowStackGCLowering.cpp43
-rw-r--r--llvm/lib/CodeGen/StackSlotColoring.cpp58
-rw-r--r--llvm/lib/CodeGen/VirtRegMap.cpp37
12 files changed, 248 insertions, 136 deletions
diff --git a/llvm/lib/CodeGen/BranchRelaxation.cpp b/llvm/lib/CodeGen/BranchRelaxation.cpp
index cbee43ecd20..2d21fbeea39 100644
--- a/llvm/lib/CodeGen/BranchRelaxation.cpp
+++ b/llvm/lib/CodeGen/BranchRelaxation.cpp
@@ -1,4 +1,4 @@
-//===-- BranchRelaxation.cpp ----------------------------------------------===//
+//===- BranchRelaxation.cpp -----------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -10,14 +10,25 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/LivePhysRegs.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/IR/DebugLoc.h"
+#include "llvm/Pass.h"
+#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/Format.h"
+#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
+#include <cassert>
+#include <cstdint>
+#include <iterator>
+#include <memory>
using namespace llvm;
@@ -30,6 +41,7 @@ STATISTIC(NumUnconditionalRelaxed, "Number of unconditional branches relaxed");
#define BRANCH_RELAX_NAME "Branch relaxation pass"
namespace {
+
class BranchRelaxation : public MachineFunctionPass {
/// BasicBlockInfo - Information about the offset and size of a single
/// basic block.
@@ -38,16 +50,16 @@ class BranchRelaxation : public MachineFunctionPass {
/// of this basic block.
///
/// The offset is always aligned as required by the basic block.
- unsigned Offset;
+ unsigned Offset = 0;
/// Size - Size of the basic block in bytes. If the block contains
/// inline assembly, this is a worst case estimate.
///
/// The size does not include any alignment padding whether from the
/// beginning of the block, or from an aligned jump table at the end.
- unsigned Size;
+ unsigned Size = 0;
- BasicBlockInfo() : Offset(0), Size(0) {}
+ BasicBlockInfo() = default;
/// Compute the offset immediately following this block. \p MBB is the next
/// block.
@@ -95,18 +107,18 @@ class BranchRelaxation : public MachineFunctionPass {
public:
static char ID;
- BranchRelaxation() : MachineFunctionPass(ID) { }
+
+ BranchRelaxation() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &MF) override;
- StringRef getPassName() const override {
- return BRANCH_RELAX_NAME;
- }
+ StringRef getPassName() const override { return BRANCH_RELAX_NAME; }
};
-}
+} // end anonymous namespace
char BranchRelaxation::ID = 0;
+
char &llvm::BranchRelaxationPassID = BranchRelaxation::ID;
INITIALIZE_PASS(BranchRelaxation, DEBUG_TYPE, BRANCH_RELAX_NAME, false, false)
@@ -196,7 +208,7 @@ void BranchRelaxation::adjustBlockOffsets(MachineBasicBlock &Start) {
}
}
- /// Insert a new empty basic block and insert it after \BB
+/// Insert a new empty basic block and insert it after \BB
MachineBasicBlock *BranchRelaxation::createNewBlockAfter(MachineBasicBlock &BB) {
// Create a new MBB for the code after the OrigBB.
MachineBasicBlock *NewBB =
@@ -233,7 +245,6 @@ MachineBasicBlock *BranchRelaxation::splitBlockBeforeInstr(MachineInstr &MI,
// Insert an entry into BlockInfo to align it properly with the block numbers.
BlockInfo.insert(BlockInfo.begin() + NewBB->getNumber(), BasicBlockInfo());
-
NewBB->transferSuccessors(OrigBB);
OrigBB->addSuccessor(NewBB);
OrigBB->addSuccessor(DestBB);
diff --git a/llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp b/llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
index fbc2bc64f42..8f88ef78828 100644
--- a/llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
+++ b/llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
@@ -1,4 +1,4 @@
-//===-- PreISelIntrinsicLowering.cpp - Pre-ISel intrinsic lowering pass ---===//
+//===- PreISelIntrinsicLowering.cpp - Pre-ISel intrinsic lowering pass ----===//
//
// The LLVM Compiler Infrastructure
//
@@ -16,15 +16,15 @@
#include "llvm/IR/Function.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/Instructions.h"
-#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/Module.h"
+#include "llvm/IR/Type.h"
+#include "llvm/IR/User.h"
#include "llvm/Pass.h"
+#include "llvm/Support/Casting.h"
using namespace llvm;
-namespace {
-
-bool lowerLoadRelative(Function &F) {
+static bool lowerLoadRelative(Function &F) {
if (F.use_empty())
return false;
@@ -55,7 +55,7 @@ bool lowerLoadRelative(Function &F) {
return Changed;
}
-bool lowerIntrinsics(Module &M) {
+static bool lowerIntrinsics(Module &M) {
bool Changed = false;
for (Function &F : M) {
if (F.getName().startswith("llvm.load.relative."))
@@ -64,23 +64,26 @@ bool lowerIntrinsics(Module &M) {
return Changed;
}
+namespace {
+
class PreISelIntrinsicLoweringLegacyPass : public ModulePass {
public:
static char ID;
+
PreISelIntrinsicLoweringLegacyPass() : ModulePass(ID) {}
- bool runOnModule(Module &M) { return lowerIntrinsics(M); }
+ bool runOnModule(Module &M) override { return lowerIntrinsics(M); }
};
+} // end anonymous namespace
+
char PreISelIntrinsicLoweringLegacyPass::ID;
-}
INITIALIZE_PASS(PreISelIntrinsicLoweringLegacyPass,
"pre-isel-intrinsic-lowering", "Pre-ISel Intrinsic Lowering",
false, false)
-namespace llvm {
-ModulePass *createPreISelIntrinsicLoweringPass() {
+ModulePass *llvm::createPreISelIntrinsicLoweringPass() {
return new PreISelIntrinsicLoweringLegacyPass;
}
@@ -91,4 +94,3 @@ PreservedAnalyses PreISelIntrinsicLoweringPass::run(Module &M,
else
return PreservedAnalyses::none();
}
-} // End llvm namespace
diff --git a/llvm/lib/CodeGen/RegAllocBase.cpp b/llvm/lib/CodeGen/RegAllocBase.cpp
index 7b4fbace2c1..a5e03f7c8de 100644
--- a/llvm/lib/CodeGen/RegAllocBase.cpp
+++ b/llvm/lib/CodeGen/RegAllocBase.cpp
@@ -1,4 +1,4 @@
-//===-- RegAllocBase.cpp - Register Allocator Base Class ------------------===//
+//===- RegAllocBase.cpp - Register Allocator Base Class -------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -14,19 +14,22 @@
#include "RegAllocBase.h"
#include "Spiller.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
-#include "llvm/CodeGen/LiveRangeEdit.h"
#include "llvm/CodeGen/LiveRegMatrix.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
+#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Timer.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetRegisterInfo.h"
+#include <cassert>
using namespace llvm;
@@ -103,7 +106,9 @@ void RegAllocBase::allocatePhysRegs() {
DEBUG(dbgs() << "\nselectOrSplit "
<< TRI->getRegClassName(MRI->getRegClass(VirtReg->reg))
<< ':' << *VirtReg << " w=" << VirtReg->weight << '\n');
- typedef SmallVector<unsigned, 4> VirtRegVec;
+
+ using VirtRegVec = SmallVector<unsigned, 4>;
+
VirtRegVec SplitVRegs;
unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs);
diff --git a/llvm/lib/CodeGen/RegAllocBase.h b/llvm/lib/CodeGen/RegAllocBase.h
index d8921b5ce6d..686ffc36e04 100644
--- a/llvm/lib/CodeGen/RegAllocBase.h
+++ b/llvm/lib/CodeGen/RegAllocBase.h
@@ -1,4 +1,4 @@
-//===-- RegAllocBase.h - basic regalloc interface and driver --*- C++ -*---===//
+//===- RegAllocBase.h - basic regalloc interface and driver -----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -37,17 +37,20 @@
#ifndef LLVM_LIB_CODEGEN_REGALLOCBASE_H
#define LLVM_LIB_CODEGEN_REGALLOCBASE_H
-#include "llvm/CodeGen/LiveInterval.h"
+#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
namespace llvm {
-template<typename T> class SmallVectorImpl;
-class TargetRegisterInfo;
-class VirtRegMap;
+class LiveInterval;
class LiveIntervals;
class LiveRegMatrix;
+class MachineInstr;
+class MachineRegisterInfo;
+template<typename T> class SmallVectorImpl;
class Spiller;
+class TargetRegisterInfo;
+class VirtRegMap;
/// RegAllocBase provides the register allocation driver and interface that can
/// be extended to add interesting heuristics.
@@ -57,12 +60,13 @@ class Spiller;
/// assignment order.
class RegAllocBase {
virtual void anchor();
+
protected:
- const TargetRegisterInfo *TRI;
- MachineRegisterInfo *MRI;
- VirtRegMap *VRM;
- LiveIntervals *LIS;
- LiveRegMatrix *Matrix;
+ const TargetRegisterInfo *TRI = nullptr;
+ MachineRegisterInfo *MRI = nullptr;
+ VirtRegMap *VRM = nullptr;
+ LiveIntervals *LIS = nullptr;
+ LiveRegMatrix *Matrix = nullptr;
RegisterClassInfo RegClassInfo;
/// Inst which is a def of an original reg and whose defs are already all
@@ -71,10 +75,8 @@ protected:
/// always available for the remat of all the siblings of the original reg.
SmallPtrSet<MachineInstr *, 32> DeadRemats;
- RegAllocBase()
- : TRI(nullptr), MRI(nullptr), VRM(nullptr), LIS(nullptr), Matrix(nullptr) {}
-
- virtual ~RegAllocBase() {}
+ RegAllocBase() = default;
+ virtual ~RegAllocBase() = default;
// A RegAlloc pass should call this before allocatePhysRegs.
void init(VirtRegMap &vrm, LiveIntervals &lis, LiveRegMatrix &mat);
@@ -120,4 +122,4 @@ private:
} // end namespace llvm
-#endif
+#endif // LLVM_LIB_CODEGEN_REGALLOCBASE_H
diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp
index fd6e602bbe4..f00a0312dad 100644
--- a/llvm/lib/CodeGen/RegAllocFast.cpp
+++ b/llvm/lib/CodeGen/RegAllocFast.cpp
@@ -1,4 +1,4 @@
-//===-- RegAllocFast.cpp - A fast register allocator for debug code -------===//
+//===- RegAllocFast.cpp - A fast register allocator for debug code --------===//
//
// The LLVM Compiler Infrastructure
//
@@ -13,27 +13,42 @@
//
//===----------------------------------------------------------------------===//
+#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/IndexedMap.h"
-#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/SparseSet.h"
#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
-#include "llvm/IR/DebugInfo.h"
+#include "llvm/IR/DebugInfoMetadata.h"
+#include "llvm/IR/DebugLoc.h"
+#include "llvm/IR/Metadata.h"
+#include "llvm/MC/MCInstrDesc.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/Pass.h"
+#include "llvm/Support/Casting.h"
+#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Target/TargetOpcodes.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
-#include <algorithm>
+#include <cassert>
+#include <tuple>
+#include <vector>
+
using namespace llvm;
#define DEBUG_TYPE "regalloc"
@@ -46,9 +61,11 @@ static RegisterRegAlloc
fastRegAlloc("fast", "fast register allocator", createFastRegisterAllocator);
namespace {
+
class RegAllocFast : public MachineFunctionPass {
public:
static char ID;
+
RegAllocFast() : MachineFunctionPass(ID), StackSlotForVirtReg(-1) {}
private:
@@ -66,27 +83,26 @@ namespace {
/// Everything we know about a live virtual register.
struct LiveReg {
- MachineInstr *LastUse; ///< Last instr to use reg.
- unsigned VirtReg; ///< Virtual register number.
- MCPhysReg PhysReg; ///< Currently held here.
- unsigned short LastOpNum; ///< OpNum on LastUse.
- bool Dirty; ///< Register needs spill.
+ MachineInstr *LastUse = nullptr; ///< Last instr to use reg.
+ unsigned VirtReg; ///< Virtual register number.
+ MCPhysReg PhysReg = 0; ///< Currently held here.
+ unsigned short LastOpNum = 0; ///< OpNum on LastUse.
+ bool Dirty = false; ///< Register needs spill.
- explicit LiveReg(unsigned v)
- : LastUse(nullptr), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false){}
+ explicit LiveReg(unsigned v) : VirtReg(v) {}
unsigned getSparseSetIndex() const {
return TargetRegisterInfo::virtReg2Index(VirtReg);
}
};
- typedef SparseSet<LiveReg> LiveRegMap;
+ using LiveRegMap = SparseSet<LiveReg>;
/// This map contains entries for each virtual register that is currently
/// available in a physical register.
LiveRegMap LiveVirtRegs;
- DenseMap<unsigned, SmallVector<MachineInstr *, 4> > LiveDbgValueMap;
+ DenseMap<unsigned, SmallVector<MachineInstr *, 4>> LiveDbgValueMap;
/// Track the state of a physical register.
enum RegState {
@@ -112,10 +128,10 @@ namespace {
std::vector<unsigned> PhysRegState;
SmallVector<unsigned, 16> VirtDead;
- SmallVector<MachineInstr*, 32> Coalesced;
+ SmallVector<MachineInstr *, 32> Coalesced;
/// Set of register units.
- typedef SparseSet<unsigned> UsedInInstrSet;
+ using UsedInInstrSet = SparseSet<unsigned>;
/// Set of register units that are used in the current instruction, and so
/// cannot be allocated.
@@ -144,6 +160,7 @@ namespace {
spillDirty = 100,
spillImpossible = ~0u
};
+
public:
StringRef getPassName() const override { return "Fast Register Allocator"; }
@@ -180,12 +197,15 @@ namespace {
void definePhysReg(MachineInstr &MI, MCPhysReg PhysReg, RegState NewState);
unsigned calcSpillCost(MCPhysReg PhysReg) const;
void assignVirtToPhysReg(LiveReg&, MCPhysReg PhysReg);
+
LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) {
return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
}
+
LiveRegMap::const_iterator findLiveVirtReg(unsigned VirtReg) const {
return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
}
+
LiveRegMap::iterator assignVirtToPhysReg(unsigned VReg, MCPhysReg PhysReg);
LiveRegMap::iterator allocVirtReg(MachineInstr &MI, LiveRegMap::iterator,
unsigned Hint);
@@ -198,8 +218,10 @@ namespace {
void dumpState();
};
- char RegAllocFast::ID = 0;
-}
+
+} // end anonymous namespace
+
+char RegAllocFast::ID = 0;
INITIALIZE_PASS(RegAllocFast, "regallocfast", "Fast Register Allocator", false,
false)
@@ -448,7 +470,6 @@ void RegAllocFast::definePhysReg(MachineInstr &MI, MCPhysReg PhysReg,
}
}
-
/// \brief Return the cost of spilling clearing out PhysReg and aliases so it is
/// free for allocation. Returns 0 when PhysReg is free or disabled with all
/// aliases disabled - it can be allocated directly.
@@ -498,7 +519,6 @@ unsigned RegAllocFast::calcSpillCost(MCPhysReg PhysReg) const {
return Cost;
}
-
/// \brief This method updates local state so that we know that PhysReg is the
/// proper container for VirtReg now. The physical register must not be used
/// for anything else when this is called.
diff --git a/llvm/lib/CodeGen/RegisterScavenging.cpp b/llvm/lib/CodeGen/RegisterScavenging.cpp
index fc5105aadbf..fdd10edf07f 100644
--- a/llvm/lib/CodeGen/RegisterScavenging.cpp
+++ b/llvm/lib/CodeGen/RegisterScavenging.cpp
@@ -16,18 +16,20 @@
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/RegisterScavenging.h"
-
+#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/LiveRegUnits.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
-#include "llvm/PassSupport.h"
+#include "llvm/Pass.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
@@ -40,6 +42,7 @@
#include <iterator>
#include <limits>
#include <string>
+#include <utility>
using namespace llvm;
@@ -769,13 +772,16 @@ void llvm::scavengeFrameVirtualRegs(MachineFunction &MF, RegScavenger &RS) {
}
namespace {
+
/// This class runs register scavenging independ of the PrologEpilogInserter.
/// This is used in for testing.
class ScavengerTest : public MachineFunctionPass {
public:
static char ID;
+
ScavengerTest() : MachineFunctionPass(ID) {}
- bool runOnMachineFunction(MachineFunction &MF) {
+
+ bool runOnMachineFunction(MachineFunction &MF) override {
const TargetSubtargetInfo &STI = MF.getSubtarget();
const TargetFrameLowering &TFL = *STI.getFrameLowering();
@@ -792,9 +798,10 @@ public:
return true;
}
};
-char ScavengerTest::ID;
} // end anonymous namespace
+char ScavengerTest::ID;
+
INITIALIZE_PASS(ScavengerTest, "scavenger-test",
"Scavenge virtual registers inside basic blocks", false, false)
diff --git a/llvm/lib/CodeGen/SafeStack.cpp b/llvm/lib/CodeGen/SafeStack.cpp
index 8584a9b7c89..8cc6bb0d95b 100644
--- a/llvm/lib/CodeGen/SafeStack.cpp
+++ b/llvm/lib/CodeGen/SafeStack.cpp
@@ -1,4 +1,4 @@
-//===-- SafeStack.cpp - Safe Stack Insertion ------------------------------===//
+//===- SafeStack.cpp - Safe Stack Insertion -------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -17,37 +17,56 @@
#include "SafeStackColoring.h"
#include "SafeStackLayout.h"
+#include "llvm/ADT/APInt.h"
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
-#include "llvm/ADT/Triple.h"
#include "llvm/Analysis/AssumptionCache.h"
#include "llvm/Analysis/BranchProbabilityInfo.h"
+#include "llvm/Analysis/LoopInfo.h"
#include "llvm/Analysis/ScalarEvolution.h"
#include "llvm/Analysis/ScalarEvolutionExpressions.h"
-#include "llvm/CodeGen/Passes.h"
+#include "llvm/Analysis/TargetLibraryInfo.h"
#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/IR/Argument.h"
+#include "llvm/IR/Attributes.h"
+#include "llvm/IR/CallSite.h"
+#include "llvm/IR/ConstantRange.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DIBuilder.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DerivedTypes.h"
+#include "llvm/IR/Dominators.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/InstIterator.h"
+#include "llvm/IR/Instruction.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/MDBuilder.h"
#include "llvm/IR/Module.h"
+#include "llvm/IR/Type.h"
+#include "llvm/IR/Use.h"
+#include "llvm/IR/User.h"
+#include "llvm/IR/Value.h"
#include "llvm/Pass.h"
-#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Casting.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Support/Format.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/Support/raw_os_ostream.h"
+#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetLowering.h"
+#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include "llvm/Transforms/Utils/Local.h"
-#include "llvm/Transforms/Utils/ModuleUtils.h"
+#include <algorithm>
+#include <cassert>
+#include <cstdint>
+#include <string>
+#include <utility>
using namespace llvm;
using namespace llvm::safestack;
@@ -255,16 +274,16 @@ bool SafeStack::IsSafeStackAlloca(const Value *AllocaPtr, uint64_t AllocaSize) {
assert(V == UI.get());
switch (I->getOpcode()) {
- case Instruction::Load: {
+ case Instruction::Load:
if (!IsAccessSafe(UI, DL.getTypeStoreSize(I->getType()), AllocaPtr,
AllocaSize))
return false;
break;
- }
+
case Instruction::VAArg:
// "va-arg" from a pointer is safe.
break;
- case Instruction::Store: {
+ case Instruction::Store:
if (V == I->getOperand(0)) {
// Stored the pointer - conservatively assume it may be unsafe.
DEBUG(dbgs() << "[SafeStack] Unsafe alloca: " << *AllocaPtr
@@ -276,11 +295,10 @@ bool SafeStack::IsSafeStackAlloca(const Value *AllocaPtr, uint64_t AllocaSize) {
AllocaPtr, AllocaSize))
return false;
break;
- }
- case Instruction::Ret: {
+
+ case Instruction::Ret:
// Information leak.
return false;
- }
case Instruction::Call:
case Instruction::Invoke: {
@@ -372,7 +390,7 @@ void SafeStack::findInsts(Function &F,
StackRestorePoints.push_back(LP);
} else if (auto II = dyn_cast<IntrinsicInst>(&I)) {
if (II->getIntrinsicID() == Intrinsic::gcroot)
- llvm::report_fatal_error(
+ report_fatal_error(
"gcroot intrinsic not compatible with safestack attribute");
}
}
@@ -764,11 +782,12 @@ bool SafeStack::run() {
}
class SafeStackLegacyPass : public FunctionPass {
- const TargetMachine *TM;
+ const TargetMachine *TM = nullptr;
public:
static char ID; // Pass identification, replacement for typeid..
- SafeStackLegacyPass() : FunctionPass(ID), TM(nullptr) {
+
+ SafeStackLegacyPass() : FunctionPass(ID) {
initializeSafeStackLegacyPassPass(*PassRegistry::getPassRegistry());
}
@@ -817,9 +836,10 @@ public:
}
};
-} // anonymous namespace
+} // end anonymous namespace
char SafeStackLegacyPass::ID = 0;
+
INITIALIZE_PASS_BEGIN(SafeStackLegacyPass, DEBUG_TYPE,
"Safe Stack instrumentation pass", false, false)
INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp
index 504ddfacd32..e398d6c18b3 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp
@@ -1,5 +1,4 @@
-//===-- llvm/CodeGen/SelectionDAGAddressAnalysis.cpp ------- DAG Address
-//Analysis ---*- C++ -*-===//
+//==- llvm/CodeGen/SelectionDAGAddressAnalysis.cpp - DAG Address Analysis --==//
//
// The LLVM Compiler Infrastructure
//
@@ -7,16 +6,18 @@
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
-//
#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/Support/Casting.h"
#include "llvm/Target/TargetLowering.h"
+#include <cstdint>
-namespace llvm {
+using namespace llvm;
bool BaseIndexOffset::equalBaseIndex(BaseIndexOffset &Other,
const SelectionDAG &DAG, int64_t &Off) {
@@ -113,4 +114,3 @@ BaseIndexOffset BaseIndexOffset::match(SDValue Ptr, const SelectionDAG &DAG) {
}
return BaseIndexOffset(Base, Index, Offset, IsIndexSignExt);
}
-} // end namespace llvm
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGTargetInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGTargetInfo.cpp
index 55f70f7d9fd..3a283bc5fdc 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGTargetInfo.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGTargetInfo.cpp
@@ -1,4 +1,4 @@
-//===-- SelectionDAGTargetInfo.cpp - SelectionDAG Info --------------------===//
+//===- SelectionDAGTargetInfo.cpp - SelectionDAG Info ---------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -12,6 +12,7 @@
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+
using namespace llvm;
-SelectionDAGTargetInfo::~SelectionDAGTargetInfo() {}
+SelectionDAGTargetInfo::~SelectionDAGTargetInfo() = default;
diff --git a/llvm/lib/CodeGen/ShadowStackGCLowering.cpp b/llvm/lib/CodeGen/ShadowStackGCLowering.cpp
index 7b60d22c7ac..25d405bf63d 100644
--- a/llvm/lib/CodeGen/ShadowStackGCLowering.cpp
+++ b/llvm/lib/CodeGen/ShadowStackGCLowering.cpp
@@ -1,4 +1,4 @@
-//===-- ShadowStackGCLowering.cpp - Custom lowering for shadow-stack gc ---===//
+//===- ShadowStackGCLowering.cpp - Custom lowering for shadow-stack gc ----===//
//
// The LLVM Compiler Infrastructure
//
@@ -16,14 +16,31 @@
//
//===----------------------------------------------------------------------===//
+#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringExtras.h"
-#include "llvm/CodeGen/GCStrategy.h"
#include "llvm/CodeGen/Passes.h"
-#include "llvm/IR/CallSite.h"
+#include "llvm/IR/BasicBlock.h"
+#include "llvm/IR/Constant.h"
+#include "llvm/IR/Constants.h"
+#include "llvm/IR/DerivedTypes.h"
+#include "llvm/IR/Function.h"
+#include "llvm/IR/GlobalValue.h"
+#include "llvm/IR/GlobalVariable.h"
#include "llvm/IR/IRBuilder.h"
+#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicInst.h"
+#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/Module.h"
+#include "llvm/IR/Type.h"
+#include "llvm/IR/Value.h"
+#include "llvm/Pass.h"
+#include "llvm/Support/Casting.h"
#include "llvm/Transforms/Utils/EscapeEnumerator.h"
+#include <cassert>
+#include <cstddef>
+#include <string>
+#include <utility>
+#include <vector>
using namespace llvm;
@@ -34,12 +51,11 @@ namespace {
class ShadowStackGCLowering : public FunctionPass {
/// RootChain - This is the global linked-list that contains the chain of GC
/// roots.
- GlobalVariable *Head;
+ GlobalVariable *Head = nullptr;
/// StackEntryTy - Abstract type of a link in the shadow stack.
- ///
- StructType *StackEntryTy;
- StructType *FrameMapTy;
+ StructType *StackEntryTy = nullptr;
+ StructType *FrameMapTy = nullptr;
/// Roots - GC roots in the current function. Each is a pair of the
/// intrinsic call and its corresponding alloca.
@@ -47,6 +63,7 @@ class ShadowStackGCLowering : public FunctionPass {
public:
static char ID;
+
ShadowStackGCLowering();
bool doInitialization(Module &M) override;
@@ -57,6 +74,7 @@ private:
Constant *GetFrameMap(Function &F);
Type *GetConcreteStackEntryType(Function &F);
void CollectRoots(Function &F);
+
static GetElementPtrInst *CreateGEP(LLVMContext &Context, IRBuilder<> &B,
Type *Ty, Value *BasePtr, int Idx1,
const char *Name);
@@ -64,7 +82,10 @@ private:
Type *Ty, Value *BasePtr, int Idx1, int Idx2,
const char *Name);
};
-}
+
+} // end anonymous namespace
+
+char ShadowStackGCLowering::ID = 0;
INITIALIZE_PASS_BEGIN(ShadowStackGCLowering, DEBUG_TYPE,
"Shadow Stack GC Lowering", false, false)
@@ -74,11 +95,7 @@ INITIALIZE_PASS_END(ShadowStackGCLowering, DEBUG_TYPE,
FunctionPass *llvm::createShadowStackGCLoweringPass() { return new ShadowStackGCLowering(); }
-char ShadowStackGCLowering::ID = 0;
-
-ShadowStackGCLowering::ShadowStackGCLowering()
- : FunctionPass(ID), Head(nullptr), StackEntryTy(nullptr),
- FrameMapTy(nullptr) {
+ShadowStackGCLowering::ShadowStackGCLowering() : FunctionPass(ID) {
initializeShadowStackGCLoweringPass(*PassRegistry::getPassRegistry());
}
diff --git a/llvm/lib/CodeGen/StackSlotColoring.cpp b/llvm/lib/CodeGen/StackSlotColoring.cpp
index 6bdff4fa2e2..8a47f3d2d6d 100644
--- a/llvm/lib/CodeGen/StackSlotColoring.cpp
+++ b/llvm/lib/CodeGen/StackSlotColoring.cpp
@@ -1,4 +1,4 @@
-//===-- StackSlotColoring.cpp - Stack slot coloring pass. -----------------===//
+//===- StackSlotColoring.cpp - Stack slot coloring pass. ------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -14,22 +14,34 @@
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/LiveStackAnalysis.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineMemOperand.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
-#include "llvm/IR/Module.h"
+#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/Pass.h"
+#include "llvm/Support/Casting.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
+#include <algorithm>
+#include <cassert>
+#include <cstdint>
+#include <iterator>
#include <vector>
+
using namespace llvm;
#define DEBUG_TYPE "stack-slot-coloring"
@@ -45,6 +57,7 @@ STATISTIC(NumEliminated, "Number of stack slots eliminated due to coloring");
STATISTIC(NumDead, "Number of trivially dead stack accesses eliminated");
namespace {
+
class StackSlotColoring : public MachineFunctionPass {
LiveStacks* LS;
MachineFrameInfo *MFI;
@@ -73,7 +86,7 @@ namespace {
BitVector AllColors;
// NextColor - Next "color" that's not yet used.
- int NextColor;
+ int NextColor = -1;
// UsedColors - "Colors" that have been assigned.
BitVector UsedColors;
@@ -83,10 +96,10 @@ namespace {
public:
static char ID; // Pass identification
- StackSlotColoring() :
- MachineFunctionPass(ID), NextColor(-1) {
- initializeStackSlotColoringPass(*PassRegistry::getPassRegistry());
- }
+
+ StackSlotColoring() : MachineFunctionPass(ID) {
+ initializeStackSlotColoringPass(*PassRegistry::getPassRegistry());
+ }
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesCFG();
@@ -111,9 +124,11 @@ namespace {
MachineFunction &MF);
bool RemoveDeadStores(MachineBasicBlock* MBB);
};
+
} // end anonymous namespace
char StackSlotColoring::ID = 0;
+
char &llvm::StackSlotColoringID = StackSlotColoring::ID;
INITIALIZE_PASS_BEGIN(StackSlotColoring, DEBUG_TYPE,
@@ -125,14 +140,16 @@ INITIALIZE_PASS_END(StackSlotColoring, DEBUG_TYPE,
"Stack Slot Coloring", false, false)
namespace {
- // IntervalSorter - Comparison predicate that sort live intervals by
- // their weight.
- struct IntervalSorter {
- bool operator()(LiveInterval* LHS, LiveInterval* RHS) const {
- return LHS->weight > RHS->weight;
- }
- };
-}
+
+// IntervalSorter - Comparison predicate that sort live intervals by
+// their weight.
+struct IntervalSorter {
+ bool operator()(LiveInterval* LHS, LiveInterval* RHS) const {
+ return LHS->weight > RHS->weight;
+ }
+};
+
+} // end anonymous namespace
/// ScanForSpillSlotRefs - Scan all the machine instructions for spill slot
/// references and update spill slot weights.
@@ -185,8 +202,10 @@ void StackSlotColoring::InitializeSlots() {
UsedColors.resize(LastFI);
Assignments.resize(LastFI);
- typedef std::iterator_traits<LiveStacks::iterator>::value_type Pair;
+ using Pair = std::iterator_traits<LiveStacks::iterator>::value_type;
+
SmallVector<Pair *, 16> Intervals;
+
Intervals.reserve(LS->getNumIntervals());
for (auto &I : *LS)
Intervals.push_back(&I);
@@ -229,7 +248,6 @@ StackSlotColoring::OverlapWithAssignments(LiveInterval *li, int Color) const {
}
/// ColorSlot - Assign a "color" (stack slot) to the specified stack slot.
-///
int StackSlotColoring::ColorSlot(LiveInterval *li) {
int Color = -1;
bool Share = false;
@@ -370,7 +388,6 @@ void StackSlotColoring::RewriteInstruction(MachineInstr &MI,
// The MachineMemOperands have already been updated.
}
-
/// RemoveDeadStores - Scan through a basic block and look for loads followed
/// by stores. If they're both using the same stack slot, then the store is
/// definitely dead. This could obviously be much more aggressive (consider
@@ -432,7 +449,6 @@ bool StackSlotColoring::RemoveDeadStores(MachineBasicBlock* MBB) {
return changed;
}
-
bool StackSlotColoring::runOnMachineFunction(MachineFunction &MF) {
DEBUG({
dbgs() << "********** Stack Slot Coloring **********\n"
diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp
index f8aacdb8649..65c62b16719 100644
--- a/llvm/lib/CodeGen/VirtRegMap.cpp
+++ b/llvm/lib/CodeGen/VirtRegMap.cpp
@@ -1,4 +1,4 @@
-//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
+//===- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map -----------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -18,24 +18,32 @@
#include "llvm/CodeGen/VirtRegMap.h"
#include "LiveDebugVariables.h"
-#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/LiveStackAnalysis.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/Passes.h"
-#include "llvm/IR/Function.h"
+#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/MC/LaneBitmask.h"
+#include "llvm/Pass.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
-#include <algorithm>
+#include <cassert>
+#include <iterator>
+#include <utility>
+
using namespace llvm;
#define DEBUG_TYPE "regalloc"
@@ -164,9 +172,9 @@ LLVM_DUMP_METHOD void VirtRegMap::dump() const {
// according to LiveIntervals.
//
namespace {
+
class VirtRegRewriter : public MachineFunctionPass {
MachineFunction *MF;
- const TargetMachine *TM;
const TargetRegisterInfo *TRI;
const TargetInstrInfo *TII;
MachineRegisterInfo *MRI;
@@ -184,18 +192,23 @@ class VirtRegRewriter : public MachineFunctionPass {
public:
static char ID;
+
VirtRegRewriter() : MachineFunctionPass(ID) {}
void getAnalysisUsage(AnalysisUsage &AU) const override;
bool runOnMachineFunction(MachineFunction&) override;
+
MachineFunctionProperties getSetProperties() const override {
return MachineFunctionProperties().set(
MachineFunctionProperties::Property::NoVRegs);
}
};
+
} // end anonymous namespace
+char VirtRegRewriter::ID = 0;
+
char &llvm::VirtRegRewriterID = VirtRegRewriter::ID;
INITIALIZE_PASS_BEGIN(VirtRegRewriter, "virtregrewriter",
@@ -208,8 +221,6 @@ INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
INITIALIZE_PASS_END(VirtRegRewriter, "virtregrewriter",
"Virtual Register Rewriter", false, false)
-char VirtRegRewriter::ID = 0;
-
void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<LiveIntervals>();
@@ -224,7 +235,6 @@ void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
MF = &fn;
- TM = &MF->getTarget();
TRI = MF->getSubtarget().getRegisterInfo();
TII = MF->getSubtarget().getInstrInfo();
MRI = &MF->getRegInfo();
@@ -260,8 +270,9 @@ void VirtRegRewriter::addLiveInsForSubRanges(const LiveInterval &LI,
assert(!LI.empty());
assert(LI.hasSubRanges());
- typedef std::pair<const LiveInterval::SubRange *,
- LiveInterval::const_iterator> SubRangeIteratorPair;
+ using SubRangeIteratorPair =
+ std::pair<const LiveInterval::SubRange *, LiveInterval::const_iterator>;
+
SmallVector<SubRangeIteratorPair, 4> SubRanges;
SlotIndex First;
SlotIndex Last;
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