diff options
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/InlineSpiller.cpp | 8 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/MachineInstrBundle.cpp | 25 |
2 files changed, 16 insertions, 17 deletions
diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp index 2408f18678e..2ebaf327c03 100644 --- a/llvm/lib/CodeGen/InlineSpiller.cpp +++ b/llvm/lib/CodeGen/InlineSpiller.cpp @@ -543,8 +543,7 @@ bool InlineSpiller::canGuaranteeAssignmentAfterRemat(unsigned VReg, bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) { // Analyze instruction SmallVector<std::pair<MachineInstr *, unsigned>, 8> Ops; - MIBundleOperands::VirtRegInfo RI = - MIBundleOperands(MI).analyzeVirtReg(VirtReg.reg, &Ops); + VirtRegInfo RI = AnalyzeVirtRegInBundle(MI, VirtReg.reg, &Ops); if (!RI.Reads) return false; @@ -782,7 +781,7 @@ static void dumpMachineInstrRangeWithSlotIndex(MachineBasicBlock::iterator B, /// foldMemoryOperand - Try folding stack slot references in Ops into their /// instructions. /// -/// @param Ops Operand indices from analyzeVirtReg(). +/// @param Ops Operand indices from AnalyzeVirtRegInBundle(). /// @param LoadMI Load instruction to use instead of stack slot when non-null. /// @return True on success. bool InlineSpiller:: @@ -992,8 +991,7 @@ void InlineSpiller::spillAroundUses(unsigned Reg) { // Analyze instruction. SmallVector<std::pair<MachineInstr*, unsigned>, 8> Ops; - MIBundleOperands::VirtRegInfo RI = - MIBundleOperands(*MI).analyzeVirtReg(Reg, &Ops); + VirtRegInfo RI = AnalyzeVirtRegInBundle(*MI, Reg, &Ops); // Find the slot index where this instruction reads and writes OldLI. // This is usually the def slot, except for tied early clobbers. diff --git a/llvm/lib/CodeGen/MachineInstrBundle.cpp b/llvm/lib/CodeGen/MachineInstrBundle.cpp index 18df5c69a22..ac9393ba8ce 100644 --- a/llvm/lib/CodeGen/MachineInstrBundle.cpp +++ b/llvm/lib/CodeGen/MachineInstrBundle.cpp @@ -278,22 +278,18 @@ bool llvm::finalizeBundles(MachineFunction &MF) { return Changed; } -//===----------------------------------------------------------------------===// -// MachineOperand iterator -//===----------------------------------------------------------------------===// - -MachineOperandIteratorBase::VirtRegInfo -MachineOperandIteratorBase::analyzeVirtReg(unsigned Reg, - SmallVectorImpl<std::pair<MachineInstr*, unsigned> > *Ops) { - VirtRegInfo RI = { false, false, false }; - for(; isValid(); ++*this) { - MachineOperand &MO = deref(); +VirtRegInfo llvm::AnalyzeVirtRegInBundle( + MachineInstr &MI, unsigned Reg, + SmallVectorImpl<std::pair<MachineInstr *, unsigned>> *Ops) { + VirtRegInfo RI = {false, false, false}; + for (MIBundleOperands O(MI); O.isValid(); ++O) { + MachineOperand &MO = *O; if (!MO.isReg() || MO.getReg() != Reg) continue; // Remember each (MI, OpNo) that refers to Reg. if (Ops) - Ops->push_back(std::make_pair(MO.getParent(), getOperandNo())); + Ops->push_back(std::make_pair(MO.getParent(), O.getOperandNo())); // Both defs and uses can read virtual registers. if (MO.readsReg()) { @@ -305,12 +301,17 @@ MachineOperandIteratorBase::analyzeVirtReg(unsigned Reg, // Only defs can write. if (MO.isDef()) RI.Writes = true; - else if (!RI.Tied && MO.getParent()->isRegTiedToDefOperand(getOperandNo())) + else if (!RI.Tied && + MO.getParent()->isRegTiedToDefOperand(O.getOperandNo())) RI.Tied = true; } return RI; } +//===----------------------------------------------------------------------===// +// MachineOperand iterator +//===----------------------------------------------------------------------===// + MachineOperandIteratorBase::PhysRegInfo MachineOperandIteratorBase::analyzePhysReg(unsigned Reg, const TargetRegisterInfo *TRI) { |
