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-rw-r--r--llvm/lib/CodeGen/InlineSpiller.cpp30
-rw-r--r--llvm/lib/CodeGen/LiveDebugVariables.cpp9
-rw-r--r--llvm/lib/CodeGen/LiveInterval.cpp12
-rw-r--r--llvm/lib/CodeGen/LiveIntervalAnalysis.cpp45
-rw-r--r--llvm/lib/CodeGen/LiveRangeCalc.cpp12
-rw-r--r--llvm/lib/CodeGen/LiveRangeEdit.cpp20
-rw-r--r--llvm/lib/CodeGen/MachineBasicBlock.cpp21
-rw-r--r--llvm/lib/CodeGen/MachineScheduler.cpp17
-rw-r--r--llvm/lib/CodeGen/MachineVerifier.cpp22
-rw-r--r--llvm/lib/CodeGen/PHIElimination.cpp19
-rw-r--r--llvm/lib/CodeGen/RegisterCoalescer.cpp52
-rw-r--r--llvm/lib/CodeGen/RegisterPressure.cpp16
-rw-r--r--llvm/lib/CodeGen/ScheduleDAGInstrs.cpp2
-rw-r--r--llvm/lib/CodeGen/SlotIndexes.cpp12
-rw-r--r--llvm/lib/CodeGen/SplitKit.cpp17
-rw-r--r--llvm/lib/CodeGen/StackColoring.cpp6
-rw-r--r--llvm/lib/CodeGen/TwoAddressInstructionPass.cpp12
-rw-r--r--llvm/lib/CodeGen/VirtRegMap.cpp4
18 files changed, 163 insertions, 165 deletions
diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp
index 1ab528a70c2..11720b9a204 100644
--- a/llvm/lib/CodeGen/InlineSpiller.cpp
+++ b/llvm/lib/CodeGen/InlineSpiller.cpp
@@ -165,7 +165,7 @@ private:
void propagateSiblingValue(SibValueMap::iterator, VNInfo *VNI = nullptr);
void analyzeSiblingValues();
- bool hoistSpill(LiveInterval &SpillLI, MachineInstr *CopyMI);
+ bool hoistSpill(LiveInterval &SpillLI, MachineInstr &CopyMI);
void eliminateRedundantSpills(LiveInterval &LI, VNInfo *VNI);
void markValueUsed(LiveInterval*, VNInfo*);
@@ -681,7 +681,7 @@ void InlineSpiller::analyzeSiblingValues() {
/// hoistSpill - Given a sibling copy that defines a value to be spilled, insert
/// a spill at a better location.
-bool InlineSpiller::hoistSpill(LiveInterval &SpillLI, MachineInstr *CopyMI) {
+bool InlineSpiller::hoistSpill(LiveInterval &SpillLI, MachineInstr &CopyMI) {
SlotIndex Idx = LIS.getInstructionIndex(CopyMI);
VNInfo *VNI = SpillLI.getVNInfoAt(Idx.getRegSlot());
assert(VNI && VNI->def == Idx.getRegSlot() && "Not defined by copy");
@@ -743,7 +743,7 @@ bool InlineSpiller::hoistSpill(LiveInterval &SpillLI, MachineInstr *CopyMI) {
TII.storeRegToStackSlot(*MBB, MII, SVI.SpillReg, false, StackSlot,
MRI.getRegClass(SVI.SpillReg), &TRI);
--MII; // Point to store instruction.
- LIS.InsertMachineInstrInMaps(MII);
+ LIS.InsertMachineInstrInMaps(*MII);
DEBUG(dbgs() << "\thoisted: " << SVI.SpillVNI->def << '\t' << *MII);
++NumSpills;
@@ -781,7 +781,7 @@ void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) {
MachineInstr *MI = &*(UI++);
if (!MI->isCopy() && !MI->mayStore())
continue;
- SlotIndex Idx = LIS.getInstructionIndex(MI);
+ SlotIndex Idx = LIS.getInstructionIndex(*MI);
if (LI->getVNInfoAt(Idx) != VNI)
continue;
@@ -860,7 +860,7 @@ bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg,
if (!RI.Reads)
return false;
- SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true);
+ SlotIndex UseIdx = LIS.getInstructionIndex(*MI).getRegSlot(true);
VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
if (!ParentVNI) {
@@ -1019,7 +1019,7 @@ bool InlineSpiller::coalesceStackAccess(MachineInstr *MI, unsigned Reg) {
return false;
DEBUG(dbgs() << "Coalescing stack access: " << *MI);
- LIS.RemoveMachineInstrFromMaps(MI);
+ LIS.RemoveMachineInstrFromMaps(*MI);
MI->eraseFromParent();
if (IsLoad) {
@@ -1051,7 +1051,7 @@ static void dumpMachineInstrRangeWithSlotIndex(MachineBasicBlock::iterator B,
dbgs() << '\t' << header << ": " << NextLine;
for (MachineBasicBlock::iterator I = B; I != E; ++I) {
- SlotIndex Idx = LIS.getInstructionIndex(I).getRegSlot();
+ SlotIndex Idx = LIS.getInstructionIndex(*I).getRegSlot();
// If a register was passed in and this instruction has it as a
// destination that is marked as an early clobber, print the
@@ -1138,18 +1138,18 @@ foldMemoryOperand(ArrayRef<std::pair<MachineInstr*, unsigned> > Ops,
continue;
// FoldMI does not define this physreg. Remove the LI segment.
assert(MO->isDead() && "Cannot fold physreg def");
- SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
+ SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
LIS.removePhysRegDefAt(Reg, Idx);
}
- LIS.ReplaceMachineInstrInMaps(MI, FoldMI);
+ LIS.ReplaceMachineInstrInMaps(*MI, *FoldMI);
MI->eraseFromParent();
// Insert any new instructions other than FoldMI into the LIS maps.
assert(!MIS.empty() && "Unexpected empty span of instructions!");
for (MachineInstr &MI : MIS)
if (&MI != FoldMI)
- LIS.InsertMachineInstrInMaps(&MI);
+ LIS.InsertMachineInstrInMaps(MI);
// TII.foldMemoryOperand may have left some implicit operands on the
// instruction. Strip them.
@@ -1252,7 +1252,7 @@ void InlineSpiller::spillAroundUses(unsigned Reg) {
// Find the slot index where this instruction reads and writes OldLI.
// This is usually the def slot, except for tied early clobbers.
- SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
+ SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
if (VNInfo *VNI = OldLI.getVNInfoAt(Idx.getRegSlot(true)))
if (SlotIndex::isSameInstr(Idx, VNI->def))
Idx = VNI->def;
@@ -1268,7 +1268,7 @@ void InlineSpiller::spillAroundUses(unsigned Reg) {
}
if (RI.Writes) {
// Hoist the spill of a sib-reg copy.
- if (hoistSpill(OldLI, MI)) {
+ if (hoistSpill(OldLI, *MI)) {
// This COPY is now dead, the value is already in the stack slot.
MI->getOperand(0).setIsDead();
DeadDefs.push_back(MI);
@@ -1349,11 +1349,11 @@ void InlineSpiller::spillAll() {
for (MachineRegisterInfo::reg_instr_iterator
RI = MRI.reg_instr_begin(Reg), E = MRI.reg_instr_end();
RI != E; ) {
- MachineInstr *MI = &*(RI++);
- assert(SnippetCopies.count(MI) && "Remaining use wasn't a snippet copy");
+ MachineInstr &MI = *(RI++);
+ assert(SnippetCopies.count(&MI) && "Remaining use wasn't a snippet copy");
// FIXME: Do this with a LiveRangeEdit callback.
LIS.RemoveMachineInstrFromMaps(MI);
- MI->eraseFromParent();
+ MI.eraseFromParent();
}
}
diff --git a/llvm/lib/CodeGen/LiveDebugVariables.cpp b/llvm/lib/CodeGen/LiveDebugVariables.cpp
index 0ca267cfafe..c95077718aa 100644
--- a/llvm/lib/CodeGen/LiveDebugVariables.cpp
+++ b/llvm/lib/CodeGen/LiveDebugVariables.cpp
@@ -520,9 +520,10 @@ bool LDVImpl::collectDebugValues(MachineFunction &mf) {
continue;
}
// DBG_VALUE has no slot index, use the previous instruction instead.
- SlotIndex Idx = MBBI == MBB->begin() ?
- LIS->getMBBStartIdx(MBB) :
- LIS->getInstructionIndex(std::prev(MBBI)).getRegSlot();
+ SlotIndex Idx =
+ MBBI == MBB->begin()
+ ? LIS->getMBBStartIdx(MBB)
+ : LIS->getInstructionIndex(*std::prev(MBBI)).getRegSlot();
// Handle consecutive DBG_VALUE instructions with the same slot index.
do {
if (handleDebugValue(MBBI, Idx)) {
@@ -614,7 +615,7 @@ UserValue::addDefsFromCopies(LiveInterval *LI, unsigned LocNo,
// Is LocNo extended to reach this copy? If not, another def may be blocking
// it, or we are looking at a wrong value of LI.
- SlotIndex Idx = LIS.getInstructionIndex(MI);
+ SlotIndex Idx = LIS.getInstructionIndex(*MI);
LocMap::iterator I = locInts.find(Idx.getRegSlot(true));
if (!I.valid() || I.value() != LocNo)
continue;
diff --git a/llvm/lib/CodeGen/LiveInterval.cpp b/llvm/lib/CodeGen/LiveInterval.cpp
index e6393200596..ab780729347 100644
--- a/llvm/lib/CodeGen/LiveInterval.cpp
+++ b/llvm/lib/CodeGen/LiveInterval.cpp
@@ -1454,9 +1454,9 @@ void ConnectedVNInfoEqClasses::Distribute(LiveInterval &LI, LiveInterval *LIV[],
// called, but it is not a requirement.
SlotIndex Idx;
if (MI->isDebugValue())
- Idx = LIS.getSlotIndexes()->getIndexBefore(MI);
+ Idx = LIS.getSlotIndexes()->getIndexBefore(*MI);
else
- Idx = LIS.getInstructionIndex(MI);
+ Idx = LIS.getInstructionIndex(*MI);
LiveQueryResult LRQ = LI.Query(Idx);
const VNInfo *VNI = MO.readsReg() ? LRQ.valueIn() : LRQ.valueDefined();
// In the case of an <undef> use that isn't tied to any def, VNI will be
@@ -1563,7 +1563,7 @@ bool ConnectedSubRegClasses::findComponents(IntEqClasses &Classes,
const LiveInterval::SubRange &SR = *SRInfo.SR;
if ((SR.LaneMask & LaneMask) == 0)
continue;
- SlotIndex Pos = LIS.getInstructionIndex(MO.getParent());
+ SlotIndex Pos = LIS.getInstructionIndex(*MO.getParent());
Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber())
: Pos.getBaseIndex();
const VNInfo *VNI = SR.getVNInfoAt(Pos);
@@ -1598,7 +1598,7 @@ void ConnectedSubRegClasses::rewriteOperands(const IntEqClasses &Classes,
MachineInstr &MI = *MO.getParent();
- SlotIndex Pos = LIS.getInstructionIndex(&MI);
+ SlotIndex Pos = LIS.getInstructionIndex(MI);
unsigned SubRegIdx = MO.getSubReg();
LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx);
@@ -1672,12 +1672,12 @@ void ConnectedSubRegClasses::computeMainRangesFixFlags(
// in and out of the instruction anymore. We need to add new dead and kill
// flags in these cases.
if (!MO.isUndef()) {
- SlotIndex Pos = LIS.getInstructionIndex(MO.getParent());
+ SlotIndex Pos = LIS.getInstructionIndex(*MO.getParent());
if (!LI->liveAt(Pos.getBaseIndex()))
MO.setIsUndef();
}
if (!MO.isDead()) {
- SlotIndex Pos = LIS.getInstructionIndex(MO.getParent());
+ SlotIndex Pos = LIS.getInstructionIndex(*MO.getParent());
if (!LI->liveAt(Pos.getDeadSlot()))
MO.setIsDead();
}
diff --git a/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp b/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
index c2426a69c8c..9b99de75560 100644
--- a/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -236,7 +236,7 @@ void LiveIntervals::computeRegMasks() {
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isRegMask())
continue;
- RegMaskSlots.push_back(Indexes->getInstructionIndex(&MI).getRegSlot());
+ RegMaskSlots.push_back(Indexes->getInstructionIndex(MI).getRegSlot());
RegMaskBits.push_back(MO.getRegMask());
}
}
@@ -247,7 +247,7 @@ void LiveIntervals::computeRegMasks() {
if (const uint32_t *Mask = MBB.getEndClobberMask(TRI)) {
assert(!MBB.empty() && "empty return block?");
RegMaskSlots.push_back(
- Indexes->getInstructionIndex(&MBB.back()).getRegSlot());
+ Indexes->getInstructionIndex(MBB.back()).getRegSlot());
RegMaskBits.push_back(Mask);
}
@@ -443,7 +443,7 @@ bool LiveIntervals::shrinkToUses(LiveInterval *li,
MachineInstr *UseMI = &*(I++);
if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
continue;
- SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
+ SlotIndex Idx = getInstructionIndex(*UseMI).getRegSlot();
LiveQueryResult LRQ = li->Query(Idx);
VNInfo *VNI = LRQ.valueIn();
if (!VNI) {
@@ -551,7 +551,7 @@ void LiveIntervals::shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg)
continue;
}
// We only need to visit each instruction once.
- SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
+ SlotIndex Idx = getInstructionIndex(*UseMI).getRegSlot();
if (Idx == LastIdx)
continue;
LastIdx = Idx;
@@ -851,14 +851,13 @@ LiveIntervals::getSpillWeight(bool isDef, bool isUse,
}
LiveRange::Segment
-LiveIntervals::addSegmentToEndOfBlock(unsigned reg, MachineInstr* startInst) {
+LiveIntervals::addSegmentToEndOfBlock(unsigned reg, MachineInstr &startInst) {
LiveInterval& Interval = createEmptyInterval(reg);
- VNInfo* VN = Interval.getNextValue(
- SlotIndex(getInstructionIndex(startInst).getRegSlot()),
- getVNInfoAllocator());
- LiveRange::Segment S(
- SlotIndex(getInstructionIndex(startInst).getRegSlot()),
- getMBBEndIdx(startInst->getParent()), VN);
+ VNInfo *VN = Interval.getNextValue(
+ SlotIndex(getInstructionIndex(startInst).getRegSlot()),
+ getVNInfoAllocator());
+ LiveRange::Segment S(SlotIndex(getInstructionIndex(startInst).getRegSlot()),
+ getMBBEndIdx(startInst.getParent()), VN);
Interval.addSegment(S);
return S;
@@ -1348,7 +1347,7 @@ private:
&& (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask) == 0)
continue;
- const MachineInstr *MI = MO.getParent();
+ const MachineInstr &MI = *MO.getParent();
SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
if (InstSlot > LastUse && InstSlot < OldIdx)
LastUse = InstSlot.getRegSlot();
@@ -1374,7 +1373,7 @@ private:
while (MII != Begin) {
if ((--MII)->isDebugValue())
continue;
- SlotIndex Idx = Indexes->getInstructionIndex(MII);
+ SlotIndex Idx = Indexes->getInstructionIndex(*MII);
// Stop searching when Before is reached.
if (!SlotIndex::isEarlierInstr(Before, Idx))
@@ -1394,9 +1393,9 @@ private:
void LiveIntervals::handleMove(MachineInstr* MI, bool UpdateFlags) {
assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
- SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
- Indexes->removeMachineInstrFromMaps(MI);
- SlotIndex NewIndex = Indexes->insertMachineInstrInMaps(MI);
+ SlotIndex OldIndex = Indexes->getInstructionIndex(*MI);
+ Indexes->removeMachineInstrFromMaps(*MI);
+ SlotIndex NewIndex = Indexes->insertMachineInstrInMaps(*MI);
assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
OldIndex < getMBBEndIdx(MI->getParent()) &&
"Cannot handle moves across basic block boundaries.");
@@ -1408,8 +1407,8 @@ void LiveIntervals::handleMove(MachineInstr* MI, bool UpdateFlags) {
void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI,
MachineInstr* BundleStart,
bool UpdateFlags) {
- SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
- SlotIndex NewIndex = Indexes->getInstructionIndex(BundleStart);
+ SlotIndex OldIndex = Indexes->getInstructionIndex(*MI);
+ SlotIndex NewIndex = Indexes->getInstructionIndex(*BundleStart);
HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
HME.updateAllRanges(MI);
}
@@ -1432,7 +1431,7 @@ void LiveIntervals::repairOldRegInRange(const MachineBasicBlock::iterator Begin,
if (MI->isDebugValue())
continue;
- SlotIndex instrIdx = getInstructionIndex(MI);
+ SlotIndex instrIdx = getInstructionIndex(*MI);
bool isStartValid = getInstructionFromIndex(LII->start);
bool isEndValid = getInstructionFromIndex(LII->end);
@@ -1509,18 +1508,18 @@ LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB,
ArrayRef<unsigned> OrigRegs) {
// Find anchor points, which are at the beginning/end of blocks or at
// instructions that already have indexes.
- while (Begin != MBB->begin() && !Indexes->hasIndex(Begin))
+ while (Begin != MBB->begin() && !Indexes->hasIndex(*Begin))
--Begin;
- while (End != MBB->end() && !Indexes->hasIndex(End))
+ while (End != MBB->end() && !Indexes->hasIndex(*End))
++End;
SlotIndex endIdx;
if (End == MBB->end())
endIdx = getMBBEndIdx(MBB).getPrevSlot();
else
- endIdx = getInstructionIndex(End);
+ endIdx = getInstructionIndex(*End);
- Indexes->repairIndexesInRange(MBB, Begin, End);
+ Indexes->repairIndexesInRange(MBB, *Begin, *End);
for (MachineBasicBlock::iterator I = End; I != Begin;) {
--I;
diff --git a/llvm/lib/CodeGen/LiveRangeCalc.cpp b/llvm/lib/CodeGen/LiveRangeCalc.cpp
index c408615d42e..4a0a5107ecf 100644
--- a/llvm/lib/CodeGen/LiveRangeCalc.cpp
+++ b/llvm/lib/CodeGen/LiveRangeCalc.cpp
@@ -42,12 +42,12 @@ void LiveRangeCalc::reset(const MachineFunction *mf,
static void createDeadDef(SlotIndexes &Indexes, VNInfo::Allocator &Alloc,
LiveRange &LR, const MachineOperand &MO) {
- const MachineInstr *MI = MO.getParent();
- SlotIndex DefIdx =
- Indexes.getInstructionIndex(MI).getRegSlot(MO.isEarlyClobber());
+ const MachineInstr &MI = *MO.getParent();
+ SlotIndex DefIdx =
+ Indexes.getInstructionIndex(MI).getRegSlot(MO.isEarlyClobber());
- // Create the def in LR. This may find an existing def.
- LR.createDeadDef(DefIdx, Alloc);
+ // Create the def in LR. This may find an existing def.
+ LR.createDeadDef(DefIdx, Alloc);
}
void LiveRangeCalc::calculate(LiveInterval &LI, bool TrackSubRegs) {
@@ -184,7 +184,7 @@ void LiveRangeCalc::extendToUses(LiveRange &LR, unsigned Reg,
// had an early-clobber flag.
isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber();
}
- UseIdx = Indexes->getInstructionIndex(MI).getRegSlot(isEarlyClobber);
+ UseIdx = Indexes->getInstructionIndex(*MI).getRegSlot(isEarlyClobber);
}
// MI is reading Reg. We may have visited MI before if it happens to be
diff --git a/llvm/lib/CodeGen/LiveRangeEdit.cpp b/llvm/lib/CodeGen/LiveRangeEdit.cpp
index 5ce364ae661..72eafcd0792 100644
--- a/llvm/lib/CodeGen/LiveRangeEdit.cpp
+++ b/llvm/lib/CodeGen/LiveRangeEdit.cpp
@@ -125,7 +125,7 @@ bool LiveRangeEdit::canRematerializeAt(Remat &RM,
// No defining instruction provided.
SlotIndex DefIdx;
if (RM.OrigMI)
- DefIdx = LIS.getInstructionIndex(RM.OrigMI);
+ DefIdx = LIS.getInstructionIndex(*RM.OrigMI);
else {
DefIdx = RM.ParentVNI->def;
RM.OrigMI = LIS.getInstructionFromIndex(DefIdx);
@@ -152,8 +152,9 @@ SlotIndex LiveRangeEdit::rematerializeAt(MachineBasicBlock &MBB,
assert(RM.OrigMI && "Invalid remat");
TII.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
Rematted.insert(RM.ParentVNI);
- return LIS.getSlotIndexes()->insertMachineInstrInMaps(--MI, Late)
- .getRegSlot();
+ return LIS.getSlotIndexes()
+ ->insertMachineInstrInMaps(*--MI, Late)
+ .getRegSlot();
}
void LiveRangeEdit::eraseVirtReg(unsigned Reg) {
@@ -188,9 +189,8 @@ bool LiveRangeEdit::foldAsLoad(LiveInterval *LI,
// Since we're moving the DefMI load, make sure we're not extending any live
// ranges.
- if (!allUsesAvailableAt(DefMI,
- LIS.getInstructionIndex(DefMI),
- LIS.getInstructionIndex(UseMI)))
+ if (!allUsesAvailableAt(DefMI, LIS.getInstructionIndex(*DefMI),
+ LIS.getInstructionIndex(*UseMI)))
return false;
// We also need to make sure it is safe to move the load.
@@ -210,7 +210,7 @@ bool LiveRangeEdit::foldAsLoad(LiveInterval *LI,
if (!FoldMI)
return false;
DEBUG(dbgs() << " folded: " << *FoldMI);
- LIS.ReplaceMachineInstrInMaps(UseMI, FoldMI);
+ LIS.ReplaceMachineInstrInMaps(*UseMI, *FoldMI);
UseMI->eraseFromParent();
DefMI->addRegisterDead(LI->reg, nullptr);
Dead.push_back(DefMI);
@@ -220,7 +220,7 @@ bool LiveRangeEdit::foldAsLoad(LiveInterval *LI,
bool LiveRangeEdit::useIsKill(const LiveInterval &LI,
const MachineOperand &MO) const {
- const MachineInstr *MI = MO.getParent();
+ const MachineInstr &MI = *MO.getParent();
SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
if (LI.Query(Idx).isKill())
return true;
@@ -237,7 +237,7 @@ bool LiveRangeEdit::useIsKill(const LiveInterval &LI,
/// Find all live intervals that need to shrink, then remove the instruction.
void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink) {
assert(MI->allDefsAreDead() && "Def isn't really dead");
- SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
+ SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
// Never delete a bundled instruction.
if (MI->isBundled()) {
@@ -316,7 +316,7 @@ void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink) {
} else {
if (TheDelegate)
TheDelegate->LRE_WillEraseInstruction(MI);
- LIS.RemoveMachineInstrFromMaps(MI);
+ LIS.RemoveMachineInstrFromMaps(*MI);
MI->eraseFromParent();
++NumDCEDeleted;
}
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
index 6421b8c9d30..de1f1c71c66 100644
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -302,16 +302,16 @@ void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
OS << '\n';
}
- for (const_instr_iterator I = instr_begin(); I != instr_end(); ++I) {
+ for (auto &I : instrs()) {
if (Indexes) {
- if (Indexes->hasIndex(&*I))
- OS << Indexes->getInstructionIndex(&*I);
+ if (Indexes->hasIndex(I))
+ OS << Indexes->getInstructionIndex(I);
OS << '\t';
}
OS << '\t';
- if (I->isInsideBundle())
+ if (I.isInsideBundle())
OS << " * ";
- I->print(OS, MST);
+ I.print(OS, MST);
}
// Print the successors of this block according to the CFG.
@@ -826,7 +826,7 @@ MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P) {
E = Terminators.end(); I != E; ++I) {
if (std::find(NewTerminators.begin(), NewTerminators.end(), *I) ==
NewTerminators.end())
- Indexes->removeMachineInstrFromMaps(*I);
+ Indexes->removeMachineInstrFromMaps(**I);
}
}
@@ -837,13 +837,12 @@ MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P) {
TII->InsertBranch(*NMBB, Succ, nullptr, Cond, DL);
if (Indexes) {
- for (instr_iterator I = NMBB->instr_begin(), E = NMBB->instr_end();
- I != E; ++I) {
+ for (MachineInstr &MI : NMBB->instrs()) {
// Some instructions may have been moved to NMBB by updateTerminator(),
// so we first remove any instruction that already has an index.
- if (Indexes->hasIndex(&*I))
- Indexes->removeMachineInstrFromMaps(&*I);
- Indexes->insertMachineInstrInMaps(&*I);
+ if (Indexes->hasIndex(MI))
+ Indexes->removeMachineInstrFromMaps(MI);
+ Indexes->insertMachineInstrInMaps(MI);
}
}
}
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index a0a10ca276c..41c757e5054 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -1039,7 +1039,7 @@ void ScheduleDAGMILive::updatePressureDiffs(
if (I == BB->end())
VNI = LI.getVNInfoBefore(LIS->getMBBEndIdx(BB));
else {
- LiveQueryResult LRQ = LI.Query(LIS->getInstructionIndex(I));
+ LiveQueryResult LRQ = LI.Query(LIS->getInstructionIndex(*I));
VNI = LRQ.valueIn();
}
// RegisterPressureTracker guarantees that readsReg is true for LiveUses.
@@ -1050,8 +1050,8 @@ void ScheduleDAGMILive::updatePressureDiffs(
// If this use comes before the reaching def, it cannot be a last use,
// so decrease its pressure change.
if (!SU->isScheduled && SU != &ExitSU) {
- LiveQueryResult LRQ
- = LI.Query(LIS->getInstructionIndex(SU->getInstr()));
+ LiveQueryResult LRQ =
+ LI.Query(LIS->getInstructionIndex(*SU->getInstr()));
if (LRQ.valueIn() == VNI) {
PressureDiff &PDiff = getPressureDiff(SU);
PDiff.addPressureChange(Reg, true, &MRI);
@@ -1243,8 +1243,7 @@ unsigned ScheduleDAGMILive::computeCyclicCriticalPath() {
continue;
// Only consider uses of the phi.
- LiveQueryResult LRQ =
- LI.Query(LIS->getInstructionIndex(SU->getInstr()));
+ LiveQueryResult LRQ = LI.Query(LIS->getInstructionIndex(*SU->getInstr()));
if (!LRQ.valueIn()->isPHIDef())
continue;
@@ -1293,7 +1292,7 @@ void ScheduleDAGMILive::scheduleMI(SUnit *SU, bool IsTopNode) {
RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, false);
if (ShouldTrackLaneMasks) {
// Adjust liveness and add missing dead+read-undef flags.
- SlotIndex SlotIdx = LIS->getInstructionIndex(MI).getRegSlot();
+ SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx, MI);
} else {
// Adjust for missing dead-def flags.
@@ -1329,7 +1328,7 @@ void ScheduleDAGMILive::scheduleMI(SUnit *SU, bool IsTopNode) {
RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, false);
if (ShouldTrackLaneMasks) {
// Adjust liveness and add missing dead+read-undef flags.
- SlotIndex SlotIdx = LIS->getInstructionIndex(MI).getRegSlot();
+ SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx, MI);
} else {
// Adjust for missing dead-def flags.
@@ -1705,9 +1704,9 @@ void CopyConstrain::apply(ScheduleDAGMI *DAG) {
MachineBasicBlock::iterator FirstPos = nextIfDebug(DAG->begin(), DAG->end());
if (FirstPos == DAG->end())
return;
- RegionBeginIdx = DAG->getLIS()->getInstructionIndex(&*FirstPos);
+ RegionBeginIdx = DAG->getLIS()->getInstructionIndex(*FirstPos);
RegionEndIdx = DAG->getLIS()->getInstructionIndex(
- &*priorNonDebug(DAG->end(), DAG->begin()));
+ *priorNonDebug(DAG->end(), DAG->begin()));
for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
SUnit *SU = &DAG->SUnits[Idx];
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 60f826069d1..8fb8921e94d 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -435,8 +435,8 @@ void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
assert(MI);
report(msg, MI->getParent());
errs() << "- instruction: ";
- if (Indexes && Indexes->hasIndex(MI))
- errs() << Indexes->getInstructionIndex(MI) << '\t';
+ if (Indexes && Indexes->hasIndex(*MI))
+ errs() << Indexes->getInstructionIndex(*MI) << '\t';
MI->print(errs(), /*SkipOpers=*/true);
errs() << '\n';
}
@@ -760,8 +760,8 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
// This function gets called for all bundle headers, including normal
// stand-alone unbundled instructions.
void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
- if (Indexes && Indexes->hasIndex(MI)) {
- SlotIndex idx = Indexes->getInstructionIndex(MI);
+ if (Indexes && Indexes->hasIndex(*MI)) {
+ SlotIndex idx = Indexes->getInstructionIndex(*MI);
if (!(idx > lastIndex)) {
report("Instruction index out of order", MI);
errs() << "Last instruction was at " << lastIndex << '\n';
@@ -849,7 +849,7 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
// Debug values must not have a slot index.
// Other instructions must have one, unless they are inside a bundle.
if (LiveInts) {
- bool mapped = !LiveInts->isNotInMIMap(MI);
+ bool mapped = !LiveInts->isNotInMIMap(*MI);
if (MI->isDebugValue()) {
if (mapped)
report("Debug instruction has a slot index", MI);
@@ -1023,10 +1023,10 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
case MachineOperand::MO_FrameIndex:
if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
- LiveInts && !LiveInts->isNotInMIMap(MI)) {
+ LiveInts && !LiveInts->isNotInMIMap(*MI)) {
int FI = MO->getIndex();
LiveInterval &LI = LiveStks->getInterval(FI);
- SlotIndex Idx = LiveInts->getInstructionIndex(MI);
+ SlotIndex Idx = LiveInts->getInstructionIndex(*MI);
bool stores = MI->mayStore();
bool loads = MI->mayLoad();
@@ -1164,8 +1164,8 @@ void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
}
// Check LiveInts liveness and kill.
- if (LiveInts && !LiveInts->isNotInMIMap(MI)) {
- SlotIndex UseIdx = LiveInts->getInstructionIndex(MI);
+ if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
+ SlotIndex UseIdx = LiveInts->getInstructionIndex(*MI);
// Check the cached regunit intervals.
if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isReserved(Reg)) {
for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
@@ -1272,8 +1272,8 @@ void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
report("Multiple virtual register defs in SSA form", MO, MONum);
// Check LiveInts for a live segment, but only for virtual registers.
- if (LiveInts && !LiveInts->isNotInMIMap(MI)) {
- SlotIndex DefIdx = LiveInts->getInstructionIndex(MI);
+ if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
+ SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI);
DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
diff --git a/llvm/lib/CodeGen/PHIElimination.cpp b/llvm/lib/CodeGen/PHIElimination.cpp
index 2c937926d0a..4e93b6ee132 100644
--- a/llvm/lib/CodeGen/PHIElimination.cpp
+++ b/llvm/lib/CodeGen/PHIElimination.cpp
@@ -159,17 +159,16 @@ bool PHIElimination::runOnMachineFunction(MachineFunction &MF) {
unsigned DefReg = DefMI->getOperand(0).getReg();
if (MRI->use_nodbg_empty(DefReg)) {
if (LIS)
- LIS->RemoveMachineInstrFromMaps(DefMI);
+ LIS->RemoveMachineInstrFromMaps(*DefMI);
DefMI->eraseFromParent();
}
}
// Clean up the lowered PHI instructions.
- for (LoweredPHIMap::iterator I = LoweredPHIs.begin(), E = LoweredPHIs.end();
- I != E; ++I) {
+ for (auto &I : LoweredPHIs) {
if (LIS)
- LIS->RemoveMachineInstrFromMaps(I->first);
- MF.DeleteMachineInstr(I->first);
+ LIS->RemoveMachineInstrFromMaps(*I.first);
+ MF.DeleteMachineInstr(I.first);
}
LoweredPHIs.clear();
@@ -310,7 +309,7 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
// Update LiveIntervals for the new copy or implicit def.
if (LIS) {
MachineInstr *NewInstr = std::prev(AfterPHIsIt);
- SlotIndex DestCopyIndex = LIS->InsertMachineInstrInMaps(NewInstr);
+ SlotIndex DestCopyIndex = LIS->InsertMachineInstrInMaps(*NewInstr);
SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB);
if (IncomingReg) {
@@ -462,8 +461,8 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
if (LIS) {
if (NewSrcInstr) {
- LIS->InsertMachineInstrInMaps(NewSrcInstr);
- LIS->addSegmentToEndOfBlock(IncomingReg, NewSrcInstr);
+ LIS->InsertMachineInstrInMaps(*NewSrcInstr);
+ LIS->addSegmentToEndOfBlock(IncomingReg, *NewSrcInstr);
}
if (!SrcUndef &&
@@ -513,7 +512,7 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
assert(KillInst->readsRegister(SrcReg) &&
"Cannot find kill instruction");
- SlotIndex LastUseIndex = LIS->getInstructionIndex(KillInst);
+ SlotIndex LastUseIndex = LIS->getInstructionIndex(*KillInst);
SrcLI.removeSegment(LastUseIndex.getRegSlot(),
LIS->getMBBEndIdx(&opBlock));
}
@@ -524,7 +523,7 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
// Really delete the PHI instruction now, if it is not in the LoweredPHIs map.
if (reusedIncoming || !IncomingReg) {
if (LIS)
- LIS->RemoveMachineInstrFromMaps(MPhi);
+ LIS->RemoveMachineInstrFromMaps(*MPhi);
MF.DeleteMachineInstr(MPhi);
}
}
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index e8793c368b2..84f6099ee99 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -467,7 +467,7 @@ bool RegisterCoalescer::adjustCopiesBackFrom(const CoalescerPair &CP,
LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
LiveInterval &IntB =
LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
- SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
+ SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI).getRegSlot();
// We have a non-trivially-coalescable copy with IntA being the source and
// IntB being the dest, thus this defines a value number in IntB. If the
@@ -642,7 +642,7 @@ bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
// BValNo is a value number in B that is defined by a copy from A. 'B1' in
// the example above.
- SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
+ SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI).getRegSlot();
VNInfo *BValNo = IntB.getVNInfoAt(CopyIdx);
assert(BValNo != nullptr && BValNo->def == CopyIdx);
@@ -692,7 +692,7 @@ bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
for (MachineOperand &MO : MRI->use_nodbg_operands(IntA.reg)) {
MachineInstr *UseMI = MO.getParent();
unsigned OpNo = &MO - &UseMI->getOperand(0);
- SlotIndex UseIdx = LIS->getInstructionIndex(UseMI);
+ SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI);
LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx);
if (US == IntA.end() || US->valno != AValNo)
continue;
@@ -716,7 +716,7 @@ bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
!MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
return false;
if (NewMI != DefMI) {
- LIS->ReplaceMachineInstrInMaps(DefMI, NewMI);
+ LIS->ReplaceMachineInstrInMaps(*DefMI, *NewMI);
MachineBasicBlock::iterator Pos = DefMI;
MBB->insert(Pos, NewMI);
MBB->erase(DefMI);
@@ -746,7 +746,7 @@ bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
UseMO.setReg(NewReg);
continue;
}
- SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true);
+ SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI).getRegSlot(true);
LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx);
assert(US != IntA.end() && "Use must be live");
if (US->valno != AValNo)
@@ -784,7 +784,7 @@ bool RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
}
ErasedInstrs.insert(UseMI);
- LIS->RemoveMachineInstrFromMaps(UseMI);
+ LIS->RemoveMachineInstrFromMaps(*UseMI);
UseMI->eraseFromParent();
}
@@ -879,7 +879,7 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
return false;
LiveInterval &SrcInt = LIS->getInterval(SrcReg);
- SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI);
+ SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI);
VNInfo *ValNo = SrcInt.Query(CopyIdx).valueIn();
assert(ValNo && "CopyMI input register not live");
if (ValNo->isPHIDef() || ValNo->isUnused())
@@ -969,7 +969,7 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
}
}
- LIS->ReplaceMachineInstrInMaps(CopyMI, NewMI);
+ LIS->ReplaceMachineInstrInMaps(*CopyMI, *NewMI);
CopyMI->eraseFromParent();
ErasedInstrs.insert(CopyMI);
@@ -1017,7 +1017,7 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
// subranges missing the definition.
LiveInterval &DstInt = LIS->getInterval(DstReg);
if (NewIdx == 0 && DstInt.hasSubRanges()) {
- SlotIndex CurrIdx = LIS->getInstructionIndex(NewMI);
+ SlotIndex CurrIdx = LIS->getInstructionIndex(*NewMI);
SlotIndex DefIndex = CurrIdx.getRegSlot(NewMI->getOperand(0).isEarlyClobber());
LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(DstReg);
VNInfo::Allocator& Alloc = LIS->getVNInfoAllocator();
@@ -1057,7 +1057,7 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
// vreg1 will see the inteferences with CL but not with CH since
// no live-ranges would have been created for ECX.
// Fix that!
- SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
+ SlotIndex NewMIIdx = LIS->getInstructionIndex(*NewMI);
for (MCRegUnitIterator Units(NewMI->getOperand(0).getReg(), TRI);
Units.isValid(); ++Units)
if (LiveRange *LR = LIS->getCachedRegUnit(*Units))
@@ -1081,7 +1081,7 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
}
}
- SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
+ SlotIndex NewMIIdx = LIS->getInstructionIndex(*NewMI);
for (unsigned i = 0, e = NewMIImplDefs.size(); i != e; ++i) {
unsigned Reg = NewMIImplDefs[i];
for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
@@ -1125,7 +1125,7 @@ bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI) {
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
isMoveInstr(*TRI, CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
- SlotIndex Idx = LIS->getInstructionIndex(CopyMI);
+ SlotIndex Idx = LIS->getInstructionIndex(*CopyMI);
const LiveInterval &SrcLI = LIS->getInterval(SrcReg);
// CopyMI is undef iff SrcReg is not live before the instruction.
if (SrcSubIdx != 0 && SrcLI.hasSubRanges()) {
@@ -1168,7 +1168,7 @@ bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI) {
if (MO.isDef() /*|| MO.isUndef()*/)
continue;
const MachineInstr &MI = *MO.getParent();
- SlotIndex UseIdx = LIS->getInstructionIndex(&MI);
+ SlotIndex UseIdx = LIS->getInstructionIndex(MI);
LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(MO.getSubReg());
bool isLive;
if (UseMask != ~0u && DstLI.hasSubRanges()) {
@@ -1218,7 +1218,7 @@ void RegisterCoalescer::updateRegDefsUses(unsigned SrcReg,
// If SrcReg wasn't read, it may still be the case that DstReg is live-in
// because SrcReg is a sub-register.
if (DstInt && !Reads && SubIdx)
- Reads = DstInt->liveAt(LIS->getInstructionIndex(UseMI));
+ Reads = DstInt->liveAt(LIS->getInstructionIndex(*UseMI));
// Replace SrcReg with DstReg in all UseMI operands.
for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
@@ -1241,8 +1241,8 @@ void RegisterCoalescer::updateRegDefsUses(unsigned SrcReg,
LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubIdx);
bool IsUndef = true;
SlotIndex MIIdx = UseMI->isDebugValue()
- ? LIS->getSlotIndexes()->getIndexBefore(UseMI)
- : LIS->getInstructionIndex(UseMI);
+ ? LIS->getSlotIndexes()->getIndexBefore(*UseMI)
+ : LIS->getInstructionIndex(*UseMI);
SlotIndex UseIdx = MIIdx.getRegSlot(true);
for (LiveInterval::SubRange &S : DstInt->subranges()) {
if ((S.LaneMask & Mask) == 0)
@@ -1273,7 +1273,7 @@ void RegisterCoalescer::updateRegDefsUses(unsigned SrcReg,
DEBUG({
dbgs() << "\t\tupdated: ";
if (!UseMI->isDebugValue())
- dbgs() << LIS->getInstructionIndex(UseMI) << "\t";
+ dbgs() << LIS->getInstructionIndex(*UseMI) << "\t";
dbgs() << *UseMI;
});
}
@@ -1299,7 +1299,7 @@ bool RegisterCoalescer::canJoinPhys(const CoalescerPair &CP) {
bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
Again = false;
- DEBUG(dbgs() << LIS->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
+ DEBUG(dbgs() << LIS->getInstructionIndex(*CopyMI) << '\t' << *CopyMI);
CoalescerPair CP(*TRI);
if (!CP.setRegisters(CopyMI)) {
@@ -1335,7 +1335,7 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
// Eliminate undefs.
if (!CP.isPhys() && eliminateUndefCopy(CopyMI)) {
- LIS->RemoveMachineInstrFromMaps(CopyMI);
+ LIS->RemoveMachineInstrFromMaps(*CopyMI);
CopyMI->eraseFromParent();
return false; // Not coalescable.
}
@@ -1346,7 +1346,7 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
if (CP.getSrcReg() == CP.getDstReg()) {
LiveInterval &LI = LIS->getInterval(CP.getSrcReg());
DEBUG(dbgs() << "\tCopy already coalesced: " << LI << '\n');
- const SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI);
+ const SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI);
LiveQueryResult LRQ = LI.Query(CopyIdx);
if (VNInfo *DefVNI = LRQ.valueDefined()) {
VNInfo *ReadVNI = LRQ.valueIn();
@@ -1364,7 +1364,7 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
}
DEBUG(dbgs() << "\tMerged values: " << LI << '\n');
}
- LIS->RemoveMachineInstrFromMaps(CopyMI);
+ LIS->RemoveMachineInstrFromMaps(*CopyMI);
CopyMI->eraseFromParent();
return true;
}
@@ -1425,7 +1425,7 @@ bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
if (!CP.isPartial() && !CP.isPhys()) {
if (adjustCopiesBackFrom(CP, CopyMI) ||
removeCopyByCommutingDef(CP, CopyMI)) {
- LIS->RemoveMachineInstrFromMaps(CopyMI);
+ LIS->RemoveMachineInstrFromMaps(*CopyMI);
CopyMI->eraseFromParent();
DEBUG(dbgs() << "\tTrivial!\n");
return true;
@@ -1539,8 +1539,8 @@ bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
MachineInstr *DestMI = MRI->getVRegDef(RHS.reg);
CopyMI = &*MRI->use_instr_nodbg_begin(RHS.reg);
- const SlotIndex CopyRegIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
- const SlotIndex DestRegIdx = LIS->getInstructionIndex(DestMI).getRegSlot();
+ const SlotIndex CopyRegIdx = LIS->getInstructionIndex(*CopyMI).getRegSlot();
+ const SlotIndex DestRegIdx = LIS->getInstructionIndex(*DestMI).getRegSlot();
// We checked above that there are no interfering defs of the physical
// register. However, for this case, where we intent to move up the def of
@@ -1576,7 +1576,7 @@ bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
}
}
- LIS->RemoveMachineInstrFromMaps(CopyMI);
+ LIS->RemoveMachineInstrFromMaps(*CopyMI);
CopyMI->eraseFromParent();
// We don't track kills for reserved registers.
@@ -2489,7 +2489,7 @@ void JoinVals::eraseInstrs(SmallPtrSetImpl<MachineInstr*> &ErasedInstrs,
}
ErasedInstrs.insert(MI);
DEBUG(dbgs() << "\t\terased:\t" << Def << '\t' << *MI);
- LIS->RemoveMachineInstrFromMaps(MI);
+ LIS->RemoveMachineInstrFromMaps(*MI);
MI->eraseFromParent();
break;
}
diff --git a/llvm/lib/CodeGen/RegisterPressure.cpp b/llvm/lib/CodeGen/RegisterPressure.cpp
index 80979267e2b..31ac34b7ade 100644
--- a/llvm/lib/CodeGen/RegisterPressure.cpp
+++ b/llvm/lib/CodeGen/RegisterPressure.cpp
@@ -271,7 +271,7 @@ SlotIndex RegPressureTracker::getCurrSlot() const {
++IdxPos;
if (IdxPos == MBB->end())
return LIS->getMBBEndIdx(MBB);
- return LIS->getInstructionIndex(IdxPos).getRegSlot();
+ return LIS->getInstructionIndex(*IdxPos).getRegSlot();
}
/// Set the boundary for the top of the region and summarize live ins.
@@ -503,7 +503,7 @@ void RegisterOperands::collect(const MachineInstr &MI,
void RegisterOperands::detectDeadDefs(const MachineInstr &MI,
const LiveIntervals &LIS) {
- SlotIndex SlotIdx = LIS.getInstructionIndex(&MI);
+ SlotIndex SlotIdx = LIS.getInstructionIndex(MI);
for (auto RI = Defs.begin(); RI != Defs.end(); /*empty*/) {
unsigned Reg = RI->RegUnit;
const LiveRange *LR = getLiveRange(LIS, Reg);
@@ -729,7 +729,7 @@ void RegPressureTracker::recede(const RegisterOperands &RegOpers,
SlotIndex SlotIdx;
if (RequireIntervals)
- SlotIdx = LIS->getInstructionIndex(CurrPos).getRegSlot();
+ SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot();
// Generate liveness for uses.
for (const RegisterMaskPair &Use : RegOpers.Uses) {
@@ -794,7 +794,7 @@ void RegPressureTracker::recedeSkipDebugValues() {
SlotIndex SlotIdx;
if (RequireIntervals)
- SlotIdx = LIS->getInstructionIndex(CurrPos).getRegSlot();
+ SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot();
// Open the top of the region using slot indexes.
if (RequireIntervals && isTopClosed())
@@ -808,7 +808,7 @@ void RegPressureTracker::recede(SmallVectorImpl<RegisterMaskPair> *LiveUses) {
RegisterOperands RegOpers;
RegOpers.collect(MI, *TRI, *MRI, TrackLaneMasks, false);
if (TrackLaneMasks) {
- SlotIndex SlotIdx = LIS->getInstructionIndex(CurrPos).getRegSlot();
+ SlotIndex SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot();
RegOpers.adjustLaneLiveness(*LIS, *MRI, SlotIdx);
} else if (RequireIntervals) {
RegOpers.detectDeadDefs(MI, *LIS);
@@ -969,7 +969,7 @@ void RegPressureTracker::bumpUpwardPressure(const MachineInstr *MI) {
SlotIndex SlotIdx;
if (RequireIntervals)
- SlotIdx = LIS->getInstructionIndex(MI).getRegSlot();
+ SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
// Account for register pressure similar to RegPressureTracker::recede().
RegisterOperands RegOpers;
@@ -1154,7 +1154,7 @@ static LaneBitmask findUseBetween(unsigned Reg, LaneBitmask LastUseMask,
if (MO.isUndef())
continue;
const MachineInstr *MI = MO.getParent();
- SlotIndex InstSlot = LIS->getInstructionIndex(MI).getRegSlot();
+ SlotIndex InstSlot = LIS->getInstructionIndex(*MI).getRegSlot();
if (InstSlot >= PriorUseIdx && InstSlot < NextUseIdx) {
unsigned SubRegIdx = MO.getSubReg();
LaneBitmask UseMask = TRI.getSubRegIndexLaneMask(SubRegIdx);
@@ -1214,7 +1214,7 @@ void RegPressureTracker::bumpDownwardPressure(const MachineInstr *MI) {
SlotIndex SlotIdx;
if (RequireIntervals)
- SlotIdx = LIS->getInstructionIndex(MI).getRegSlot();
+ SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
// Account for register pressure similar to RegPressureTracker::recede().
RegisterOperands RegOpers;
diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
index aab3184c58a..66e83f802cc 100644
--- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -929,7 +929,7 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
RegisterOperands RegOpers;
RegOpers.collect(*MI, *TRI, MRI, TrackLaneMasks, false);
if (TrackLaneMasks) {
- SlotIndex SlotIdx = LIS->getInstructionIndex(MI);
+ SlotIndex SlotIdx = LIS->getInstructionIndex(*MI);
RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx);
}
if (PDiffs != nullptr)
diff --git a/llvm/lib/CodeGen/SlotIndexes.cpp b/llvm/lib/CodeGen/SlotIndexes.cpp
index f96b2a604e5..f0713efee3f 100644
--- a/llvm/lib/CodeGen/SlotIndexes.cpp
+++ b/llvm/lib/CodeGen/SlotIndexes.cpp
@@ -150,9 +150,9 @@ void SlotIndexes::repairIndexesInRange(MachineBasicBlock *MBB,
// does the same thing.
// Find anchor points, which are at the beginning/end of blocks or at
// instructions that already have indexes.
- while (Begin != MBB->begin() && !hasIndex(Begin))
+ while (Begin != MBB->begin() && !hasIndex(*Begin))
--Begin;
- while (End != MBB->end() && !hasIndex(End))
+ while (End != MBB->end() && !hasIndex(*End))
++End;
bool includeStart = (Begin == MBB->begin());
@@ -160,13 +160,13 @@ void SlotIndexes::repairIndexesInRange(MachineBasicBlock *MBB,
if (includeStart)
startIdx = getMBBStartIdx(MBB);
else
- startIdx = getInstructionIndex(Begin);
+ startIdx = getInstructionIndex(*Begin);
SlotIndex endIdx;
if (End == MBB->end())
endIdx = getMBBEndIdx(MBB);
else
- endIdx = getInstructionIndex(End);
+ endIdx = getInstructionIndex(*End);
// FIXME: Conceptually, this code is implementing an iterator on MBB that
// optionally includes an additional position prior to MBB->begin(), indicated
@@ -199,7 +199,7 @@ void SlotIndexes::repairIndexesInRange(MachineBasicBlock *MBB,
} else {
--ListI;
if (SlotMI)
- removeMachineInstrFromMaps(SlotMI);
+ removeMachineInstrFromMaps(*SlotMI);
}
}
@@ -209,7 +209,7 @@ void SlotIndexes::repairIndexesInRange(MachineBasicBlock *MBB,
--I;
MachineInstr *MI = I;
if (!MI->isDebugValue() && mi2iMap.find(MI) == mi2iMap.end())
- insertMachineInstrInMaps(MI);
+ insertMachineInstrInMaps(*MI);
}
}
diff --git a/llvm/lib/CodeGen/SplitKit.cpp b/llvm/lib/CodeGen/SplitKit.cpp
index 854fd4b9eea..5be82b85272 100644
--- a/llvm/lib/CodeGen/SplitKit.cpp
+++ b/llvm/lib/CodeGen/SplitKit.cpp
@@ -68,7 +68,7 @@ SlotIndex SplitAnalysis::computeLastSplitPoint(unsigned Num) {
if (FirstTerm == MBB->end())
LSP.first = MBBEnd;
else
- LSP.first = LIS.getInstructionIndex(FirstTerm);
+ LSP.first = LIS.getInstructionIndex(*FirstTerm);
// If there is a landing pad successor, also find the call instruction.
if (!LPad)
@@ -79,7 +79,7 @@ SlotIndex SplitAnalysis::computeLastSplitPoint(unsigned Num) {
I != E;) {
--I;
if (I->isCall()) {
- LSP.second = LIS.getInstructionIndex(I);
+ LSP.second = LIS.getInstructionIndex(*I);
break;
}
}
@@ -129,7 +129,7 @@ void SplitAnalysis::analyzeUses() {
const MachineRegisterInfo &MRI = MF.getRegInfo();
for (MachineOperand &MO : MRI.use_nodbg_operands(CurLI->reg))
if (!MO.isUndef())
- UseSlots.push_back(LIS.getInstructionIndex(MO.getParent()).getRegSlot());
+ UseSlots.push_back(LIS.getInstructionIndex(*MO.getParent()).getRegSlot());
array_pod_sort(UseSlots.begin(), UseSlots.end());
@@ -438,8 +438,9 @@ VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
// Can't remat, just insert a copy from parent.
CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg)
.addReg(Edit->getReg());
- Def = LIS.getSlotIndexes()->insertMachineInstrInMaps(CopyMI, Late)
- .getRegSlot();
+ Def = LIS.getSlotIndexes()
+ ->insertMachineInstrInMaps(*CopyMI, Late)
+ .getRegSlot();
++NumCopies;
}
@@ -638,7 +639,7 @@ void SplitEditor::removeBackCopies(SmallVectorImpl<VNInfo*> &Copies) {
DEBUG(dbgs() << "Removing " << Def << '\t' << *MI);
LIS.removeVRegDefAt(*LI, Def);
- LIS.RemoveMachineInstrFromMaps(MI);
+ LIS.RemoveMachineInstrFromMaps(*MI);
MI->eraseFromParent();
// Adjust RegAssign if a register assignment is killed at Def. We want to
@@ -654,7 +655,7 @@ void SplitEditor::removeBackCopies(SmallVectorImpl<VNInfo*> &Copies) {
DEBUG(dbgs() << " cannot find simple kill of RegIdx " << RegIdx << '\n');
forceRecompute(RegIdx, Edit->getParent().getVNInfoAt(Def));
} else {
- SlotIndex Kill = LIS.getInstructionIndex(MBBI).getRegSlot();
+ SlotIndex Kill = LIS.getInstructionIndex(*MBBI).getRegSlot();
DEBUG(dbgs() << " move kill to " << Kill << '\t' << *MBBI);
AssignI.setStop(Kill);
}
@@ -964,7 +965,7 @@ void SplitEditor::rewriteAssigned(bool ExtendRanges) {
// <undef> operands don't really read the register, so it doesn't matter
// which register we choose. When the use operand is tied to a def, we must
// use the same register as the def, so just do that always.
- SlotIndex Idx = LIS.getInstructionIndex(MI);
+ SlotIndex Idx = LIS.getInstructionIndex(*MI);
if (MO.isDef() || MO.isUndef())
Idx = Idx.getRegSlot(MO.isEarlyClobber());
diff --git a/llvm/lib/CodeGen/StackColoring.cpp b/llvm/lib/CodeGen/StackColoring.cpp
index 30032b18e2f..984ce470c6f 100644
--- a/llvm/lib/CodeGen/StackColoring.cpp
+++ b/llvm/lib/CodeGen/StackColoring.cpp
@@ -395,7 +395,7 @@ void StackColoring::calculateLiveIntervals(unsigned NumSlots) {
int Slot = Mo.getIndex();
assert(Slot >= 0 && "Invalid slot");
- SlotIndex ThisIndex = Indexes->getInstructionIndex(MI);
+ SlotIndex ThisIndex = Indexes->getInstructionIndex(*MI);
if (IsStart) {
if (!Starts[Slot].isValid() || Starts[Slot] > ThisIndex)
@@ -569,7 +569,7 @@ void StackColoring::remapInstructions(DenseMap<int, int> &SlotRemap) {
// If we *don't* protect the user from escaped allocas, don't bother
// validating the instructions.
if (!I.isDebugValue() && TouchesMemory && ProtectFromEscapedAllocas) {
- SlotIndex Index = Indexes->getInstructionIndex(&I);
+ SlotIndex Index = Indexes->getInstructionIndex(I);
const LiveInterval *Interval = &*Intervals[FromSlot];
assert(Interval->find(Index) != Interval->end() &&
"Found instruction usage outside of live range.");
@@ -628,7 +628,7 @@ void StackColoring::removeInvalidSlotRanges() {
// Check that the used slot is inside the calculated lifetime range.
// If it is not, warn about it and invalidate the range.
LiveInterval *Interval = &*Intervals[Slot];
- SlotIndex Index = Indexes->getInstructionIndex(&I);
+ SlotIndex Index = Indexes->getInstructionIndex(I);
if (Interval->find(Index) == Interval->end()) {
Interval->clear();
DEBUG(dbgs()<<"Invalidating range #"<<Slot<<"\n");
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index e8009cc8337..30bcb6da62e 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -401,7 +401,7 @@ static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg,
LiveIntervals *LIS) {
if (LIS && TargetRegisterInfo::isVirtualRegister(Reg) &&
- !LIS->isNotInMIMap(MI)) {
+ !LIS->isNotInMIMap(*MI)) {
// FIXME: Sometimes tryInstructionTransform() will add instructions and
// test whether they can be folded before keeping them. In this case it
// sets a kill before recursively calling tryInstructionTransform() again.
@@ -414,7 +414,7 @@ static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg,
if (!LI.hasAtLeastOneValue())
return false;
- SlotIndex useIdx = LIS->getInstructionIndex(MI);
+ SlotIndex useIdx = LIS->getInstructionIndex(*MI);
LiveInterval::const_iterator I = LI.find(useIdx);
assert(I != LI.end() && "Reg must be live-in to use.");
return !I->end.isBlock() && SlotIndex::isSameInstr(I->end, useIdx);
@@ -706,7 +706,7 @@ TwoAddressInstructionPass::convertInstTo3Addr(MachineBasicBlock::iterator &mi,
bool Sunk = false;
if (LIS)
- LIS->ReplaceMachineInstrInMaps(mi, NewMI);
+ LIS->ReplaceMachineInstrInMaps(*mi, *NewMI);
if (NewMI->findRegisterUseOperand(RegB, false, TRI))
// FIXME: Temporary workaround. If the new instruction doesn't
@@ -1521,13 +1521,13 @@ TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI,
DistanceMap[MI] = ++Dist;
if (LIS) {
- LastCopyIdx = LIS->InsertMachineInstrInMaps(PrevMI).getRegSlot();
+ LastCopyIdx = LIS->InsertMachineInstrInMaps(*PrevMI).getRegSlot();
if (TargetRegisterInfo::isVirtualRegister(RegA)) {
LiveInterval &LI = LIS->getInterval(RegA);
VNInfo *VNI = LI.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator());
SlotIndex endIdx =
- LIS->getInstructionIndex(MI).getRegSlot(IsEarlyClobber);
+ LIS->getInstructionIndex(*MI).getRegSlot(IsEarlyClobber);
LI.addSegment(LiveInterval::Segment(LastCopyIdx, endIdx, VNI));
}
}
@@ -1582,7 +1582,7 @@ TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI,
// Update LiveIntervals.
if (LIS) {
LiveInterval &LI = LIS->getInterval(RegB);
- SlotIndex MIIdx = LIS->getInstructionIndex(MI);
+ SlotIndex MIIdx = LIS->getInstructionIndex(*MI);
LiveInterval::const_iterator I = LI.find(MIIdx);
assert(I != LI.end() && "RegB must be live-in to use.");
diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp
index e95cc6caf96..6c7493d17cb 100644
--- a/llvm/lib/CodeGen/VirtRegMap.cpp
+++ b/llvm/lib/CodeGen/VirtRegMap.cpp
@@ -329,7 +329,7 @@ bool VirtRegRewriter::readsUndefSubreg(const MachineOperand &MO) const {
unsigned Reg = MO.getReg();
const LiveInterval &LI = LIS->getInterval(Reg);
const MachineInstr &MI = *MO.getParent();
- SlotIndex BaseIndex = LIS->getInstructionIndex(&MI);
+ SlotIndex BaseIndex = LIS->getInstructionIndex(MI);
// This code is only meant to handle reading undefined subregisters which
// we couldn't properly detect before.
assert(LI.liveAt(BaseIndex) &&
@@ -438,7 +438,7 @@ void VirtRegRewriter::rewrite() {
++NumIdCopies;
DEBUG(dbgs() << "Deleting identity copy.\n");
if (Indexes)
- Indexes->removeMachineInstrFromMaps(MI);
+ Indexes->removeMachineInstrFromMaps(*MI);
// It's safe to erase MI because MII has already been incremented.
MI->eraseFromParent();
}
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