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-rw-r--r--llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp2
-rw-r--r--llvm/lib/CodeGen/LowLevelType.cpp9
-rw-r--r--llvm/lib/CodeGen/MIRParser/MIParser.cpp6
-rw-r--r--llvm/lib/CodeGen/MachineRegisterInfo.cpp2
-rw-r--r--llvm/lib/CodeGen/MachineVerifier.cpp2
5 files changed, 8 insertions, 13 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
index 1f342ee5622..20015ae82fd 100644
--- a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
@@ -367,7 +367,7 @@ unsigned RegisterBankInfo::getSizeInBits(unsigned Reg,
RC = TRI.getMinimalPhysRegClass(Reg);
} else {
LLT Ty = MRI.getType(Reg);
- unsigned RegSize = Ty.isSized() ? Ty.getSizeInBits() : 0;
+ unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0;
// If Reg is not a generic register, query the register class to
// get its size.
if (RegSize)
diff --git a/llvm/lib/CodeGen/LowLevelType.cpp b/llvm/lib/CodeGen/LowLevelType.cpp
index 819d85aae5b..fd235f2cfd1 100644
--- a/llvm/lib/CodeGen/LowLevelType.cpp
+++ b/llvm/lib/CodeGen/LowLevelType.cpp
@@ -35,7 +35,7 @@ LLT::LLT(Type &Ty, const DataLayout &DL) {
ElementsOrAddrSpace = 1;
assert(SizeInBits != 0 && "invalid zero-sized type");
} else {
- Kind = Unsized;
+ Kind = Invalid;
SizeInBits = ElementsOrAddrSpace = 0;
}
}
@@ -45,10 +45,9 @@ void LLT::print(raw_ostream &OS) const {
OS << "<" << ElementsOrAddrSpace << " x s" << SizeInBits << ">";
else if (isPointer())
OS << "p" << getAddressSpace();
- else if (isSized())
+ else if (isValid()) {
+ assert(isScalar() && "unexpected type");
OS << "s" << getScalarSizeInBits();
- else if (isValid())
- OS << "unsized";
- else
+ } else
llvm_unreachable("trying to print an invalid type");
}
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index 6fb3d281be0..2f4410ba7cd 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1039,11 +1039,7 @@ bool MIParser::parseIRConstant(StringRef::iterator Loc, const Constant *&C) {
}
bool MIParser::parseLowLevelType(StringRef::iterator Loc, LLT &Ty) {
- if (Token.is(MIToken::Identifier) && Token.stringValue() == "unsized") {
- lex();
- Ty = LLT::unsized();
- return false;
- } else if (Token.is(MIToken::ScalarType)) {
+ if (Token.is(MIToken::ScalarType)) {
Ty = LLT::scalar(APSInt(Token.range().drop_front()).getZExtValue());
lex();
return false;
diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
index ca89a1ff7bc..55306dd6727 100644
--- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
@@ -143,7 +143,7 @@ void MachineRegisterInfo::clearVirtRegTypes() {
// Verify that the size of the now-constrained vreg is unchanged.
for (auto &VRegToType : getVRegToType()) {
auto *RC = getRegClass(VRegToType.first);
- if (VRegToType.second.isSized() &&
+ if (VRegToType.second.isValid() &&
VRegToType.second.getSizeInBits() > (RC->getSize() * 8))
llvm_unreachable(
"Virtual register has explicit size different from its class size");
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 808f81a567b..33bf9abc8ef 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1051,7 +1051,7 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
}
// Make sure the register fits into its register bank if any.
- if (RegBank && Ty.isSized() &&
+ if (RegBank && Ty.isValid() &&
RegBank->getSize() < Ty.getSizeInBits()) {
report("Register bank is too small for virtual register", MO,
MONum);
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