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-rw-r--r--llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index dc61577d6a3..4af854ec0c9 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -2413,7 +2413,6 @@ bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
SDValue DAGTypeLegalizer::WidenVecOp_ZERO_EXTEND(SDNode *N) {
SDLoc DL(N);
EVT VT = N->getValueType(0);
- unsigned NumElts = VT.getVectorNumElements();
SDValue InOp = N->getOperand(0);
// If some legalization strategy other than widening is used on the operand,
@@ -2422,8 +2421,9 @@ SDValue DAGTypeLegalizer::WidenVecOp_ZERO_EXTEND(SDNode *N) {
if (getTypeAction(InOp.getValueType()) != TargetLowering::TypeWidenVector)
return WidenVecOp_Convert(N);
InOp = GetWidenedVector(InOp);
- EVT InVT = InOp.getValueType();
- assert(NumElts < InVT.getVectorNumElements() && "Input wasn't widened!");
+ assert(VT.getVectorNumElements() <
+ InOp.getValueType().getVectorNumElements() &&
+ "Input wasn't widened!");
// Use a special DAG node to represent the operation of zero extending the
// low lanes.
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