diff options
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/AsmPrinter.cpp | 11 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp | 11 |
2 files changed, 18 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter.cpp index 34394608807..c00d4d197c8 100644 --- a/llvm/lib/CodeGen/AsmPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter.cpp @@ -29,6 +29,7 @@ #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/ADT/SmallPtrSet.h" #include <cerrno> using namespace llvm; @@ -39,7 +40,8 @@ AsmVerbose("asm-verbose", cl::Hidden, cl::desc("Add comments to directives.")); char AsmPrinter::ID = 0; AsmPrinter::AsmPrinter(std::ostream &o, TargetMachine &tm, const TargetAsmInfo *T) - : MachineFunctionPass((intptr_t)&ID), FunctionNumber(0), O(o), TM(tm), TAI(T), + : MachineFunctionPass((intptr_t)&ID), FunctionNumber(0), O(o), + TM(tm), TAI(T), TRI(tm.getRegisterInfo()), IsInTextSection(false) {} @@ -1294,6 +1296,13 @@ void AsmPrinter::printInlineAsm(const MachineInstr *MI) const { O << "\n\t" << TAI->getInlineAsmEnd() << "\n"; } +/// printImplicitDef - This method prints the specified machine instruction +/// that is an implicit def. +void AsmPrinter::printImplicitDef(const MachineInstr *MI) const { + O << "\t" << TAI->getCommentString() << " implicit-def: " + << TRI->getAsmName(MI->getOperand(0).getReg()) << "\n"; +} + /// printLabel - This method prints a local label used by debug and /// exception handling tables. void AsmPrinter::printLabel(const MachineInstr *MI) const { diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index 45237756a8d..d0d078ab133 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -467,8 +467,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo, assert(isNew && "Node emitted out of order - early"); } -void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, - MachineInstr *MI, +void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI, const TargetInstrDesc &II, DenseMap<SDOperand, unsigned> &VRBaseMap) { for (unsigned i = 0; i < II.getNumDefs(); ++i) { @@ -494,7 +493,13 @@ void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, // Create the result registers for this node and add the result regs to // the machine instruction. if (VRBase == 0) { - const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TII, II, i); + const TargetRegisterClass *RC; + if (Node->getTargetOpcode() == TargetInstrInfo::IMPLICIT_DEF) + // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc + // does not include operand register class info. + RC = DAG.getTargetLoweringInfo().getRegClassFor(Node->getValueType(0)); + else + RC = getInstrOperandRegClass(TRI, TII, II, i); assert(RC && "Isn't a register operand!"); VRBase = MRI.createVirtualRegister(RC); MI->addOperand(MachineOperand::CreateReg(VRBase, true)); |
