1 files changed, 8 insertions, 46 deletions

diff --git a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
index 8287a15e01d..6e8307917c7 100644
--- a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
@@ -19,9 +19,7 @@
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetOpcodes.h"
 #include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
 
 #include <algorithm> // For std::max.
 
@@ -29,40 +27,6 @@
 
 using namespace llvm;
 
-const unsigned RegisterBankInfo::DefaultMappingID = UINT_MAX;
-const unsigned RegisterBankInfo::InvalidMappingID = UINT_MAX - 1;
-
-/// Get the size in bits of the \p OpIdx-th operand of \p MI.
-///
-/// \pre \p MI is part of a basic block and this basic block is part
-/// of a function.
-static unsigned getSizeInBits(const MachineInstr &MI, unsigned OpIdx) {
-  unsigned Reg = MI.getOperand(OpIdx).getReg();
-  const TargetRegisterClass *RC = nullptr;
-  if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
-    const TargetSubtargetInfo &STI =
-        MI.getParent()->getParent()->getSubtarget();
-    const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
-    // The size is not directly available for physical registers.
-    // Instead, we need to access a register class that contains Reg and
-    // get the size of that register class.
-    RC = TRI.getMinimalPhysRegClass(Reg);
-  } else {
-    const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
-    unsigned RegSize = MRI.getSize(Reg);
-    // If Reg is not a generic register, query the register class to
-    // get its size.
-    if (RegSize)
-      return RegSize;
-    RC = MRI.getRegClass(Reg);
-  }
-  assert(RC && "Unable to deduce the register class");
-  return RC->getSize() * 8;
-}
-
-//------------------------------------------------------------------------------
-// RegisterBankInfo implementation.
-//------------------------------------------------------------------------------
 RegisterBankInfo::RegisterBankInfo(unsigned NumRegBanks)
     : NumRegBanks(NumRegBanks) {
   RegBanks.reset(new RegisterBank[NumRegBanks]);
@@ -212,14 +176,6 @@ void RegisterBankInfo::addRegBankCoverage(unsigned ID, unsigned RCId,
   } while (!WorkList.empty());
 }
 
-RegisterBankInfo::InstructionMapping
-RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
-  if (MI.getOpcode() > TargetOpcode::GENERIC_OP_END) {
-    // TODO.
-  }
-  llvm_unreachable("The target must implement this");
-}
-
 //------------------------------------------------------------------------------
 // Helper classes implementation.
 //------------------------------------------------------------------------------
@@ -278,6 +234,7 @@ void RegisterBankInfo::ValueMapping::verify(unsigned ExpectedBitWidth) const {
 void RegisterBankInfo::InstructionMapping::verify(
     const MachineInstr &MI) const {
   // Check that all the register operands are properly mapped.
+  const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
   // Check the constructor invariant.
   assert(NumOperands == MI.getNumOperands() &&
          "NumOperands must match, see constructor");
@@ -289,9 +246,14 @@ void RegisterBankInfo::InstructionMapping::verify(
              "We should not care about non-reg mapping");
       continue;
     }
+    unsigned Reg = MO.getReg();
     // Register size in bits.
-    // This size must match what the mapping expects.
-    unsigned RegSize = getSizeInBits(MI, Idx);
+    // This size must match what the mapping expect.
+    unsigned RegSize = MRI.getSize(Reg);
+    // If Reg is not a generic register, query the register class to
+    // get its size.
+    if (!RegSize)
+      RegSize = MRI.getRegClass(Reg)->getSize() * 8;
     MOMapping.verify(RegSize);
   }
 }