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-rw-r--r--llvm/lib/CodeGen/TargetSchedule.cpp5
1 files changed, 2 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/TargetSchedule.cpp b/llvm/lib/CodeGen/TargetSchedule.cpp
index f5181a362d7..19300070dfb 100644
--- a/llvm/lib/CodeGen/TargetSchedule.cpp
+++ b/llvm/lib/CodeGen/TargetSchedule.cpp
@@ -267,11 +267,10 @@ TargetSchedModel::computeInstrLatency(const MachineInstr *MI,
unsigned TargetSchedModel::
computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
const MachineInstr *DepMI) const {
- if (SchedModel.MicroOpBufferSize <= 1)
+ if (!SchedModel.isOutOfOrder())
return 1;
- // MicroOpBufferSize > 1 indicates an out-of-order processor that can dispatch
- // WAW dependencies in the same cycle.
+ // Out-of-order processor can dispatch WAW dependencies in the same cycle.
// Treat predication as a data dependency for out-of-order cpus. In-order
// cpus do not need to treat predicated writes specially.
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