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-rw-r--r--llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp16
1 files changed, 16 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index fa73684399b..f2a43e62f18 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1787,6 +1787,22 @@ bool TargetLowering::SimplifyDemandedVectorElts(
KnownUndef &= SrcUndef;
break;
}
+ case ISD::AND: {
+ APInt SrcUndef, SrcZero;
+ if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedElts, SrcUndef,
+ SrcZero, TLO, Depth + 1))
+ return true;
+ if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, KnownUndef,
+ KnownZero, TLO, Depth + 1))
+ return true;
+
+ // If either side has a zero element, then the result element is zero, even
+ // if the other is an UNDEF.
+ KnownZero |= SrcZero;
+ KnownUndef &= SrcUndef;
+ KnownUndef &= ~KnownZero;
+ break;
+ }
case ISD::TRUNCATE:
case ISD::SIGN_EXTEND:
case ISD::ZERO_EXTEND:
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