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-rw-r--r--llvm/lib/CodeGen/SelectionDAG/FastISel.cpp17
1 files changed, 9 insertions, 8 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
index a6212aa49ea..98022dc8e45 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -1712,14 +1712,11 @@ void FastISel::finishCondBranch(const BasicBlock *BranchBB,
}
/// Emit an FNeg operation.
-bool FastISel::selectFNeg(const User *I) {
- Value *X;
- if (!match(I, m_FNeg(m_Value(X))))
- return false;
- unsigned OpReg = getRegForValue(X);
+bool FastISel::selectFNeg(const User *I, const Value *In) {
+ unsigned OpReg = getRegForValue(In);
if (!OpReg)
return false;
- bool OpRegIsKill = hasTrivialKill(X);
+ bool OpRegIsKill = hasTrivialKill(In);
// If the target has ISD::FNEG, use it.
EVT VT = TLI.getValueType(DL, I->getType());
@@ -1806,9 +1803,13 @@ bool FastISel::selectOperator(const User *I, unsigned Opcode) {
return selectBinaryOp(I, ISD::FADD);
case Instruction::Sub:
return selectBinaryOp(I, ISD::SUB);
- case Instruction::FSub:
+ case Instruction::FSub: {
// FNeg is currently represented in LLVM IR as a special case of FSub.
- return selectFNeg(I) || selectBinaryOp(I, ISD::FSUB);
+ Value *X;
+ if (match(I, m_FNeg(m_Value(X))))
+ return selectFNeg(I, X);
+ return selectBinaryOp(I, ISD::FSUB);
+ }
case Instruction::Mul:
return selectBinaryOp(I, ISD::MUL);
case Instruction::FMul:
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