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-rw-r--r--llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp64
1 files changed, 32 insertions, 32 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 9b2bf7f88ad..34998d6fd85 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -181,7 +181,7 @@ namespace {
/// if things it uses can be simplified by bit propagation.
/// If so, return true.
bool SimplifyDemandedBits(SDValue Op) {
- unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
+ unsigned BitWidth = Op.getValueType().getScalarSizeInBits();
APInt Demanded = APInt::getAllOnesValue(BitWidth);
return SimplifyDemandedBits(Op, Demanded);
}
@@ -1754,7 +1754,7 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
if (N1.getOpcode() == ISD::AND) {
SDValue AndOp0 = N1.getOperand(0);
unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
- unsigned DestBits = VT.getScalarType().getSizeInBits();
+ unsigned DestBits = VT.getScalarSizeInBits();
// (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
// and similar xforms where the inner op is either ~0 or 0.
@@ -2058,7 +2058,7 @@ SDValue DAGCombiner::visitMUL(SDNode *N) {
// We require a splat of the entire scalar bit width for non-contiguous
// bit patterns.
bool IsFullSplat =
- ConstValue1.getBitWidth() == VT.getScalarType().getSizeInBits();
+ ConstValue1.getBitWidth() == VT.getScalarSizeInBits();
// fold (mul x, 1) -> x
if (N1IsConst && ConstValue1 == 1 && IsFullSplat)
return N0;
@@ -3082,13 +3082,13 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
// do not return N0, because undef node may exist in N0
return DAG.getConstant(
APInt::getNullValue(
- N0.getValueType().getScalarType().getSizeInBits()),
+ N0.getValueType().getScalarSizeInBits()),
SDLoc(N), N0.getValueType());
if (ISD::isBuildVectorAllZeros(N1.getNode()))
// do not return N1, because undef node may exist in N1
return DAG.getConstant(
APInt::getNullValue(
- N1.getValueType().getScalarType().getSizeInBits()),
+ N1.getValueType().getScalarSizeInBits()),
SDLoc(N), N1.getValueType());
// fold (and x, -1) -> x, vector edition
@@ -3111,7 +3111,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
if (isAllOnesConstant(N1))
return N0;
// if (and x, c) is known to be zero, return 0
- unsigned BitWidth = VT.getScalarType().getSizeInBits();
+ unsigned BitWidth = VT.getScalarSizeInBits();
if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
APInt::getAllOnesValue(BitWidth)))
return DAG.getConstant(0, SDLoc(N), VT);
@@ -3178,7 +3178,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
// that will apply equally to all members of the vector, so AND all the
// lanes of the constant together.
EVT VT = Vector->getValueType(0);
- unsigned BitWidth = VT.getScalarType().getSizeInBits();
+ unsigned BitWidth = VT.getScalarSizeInBits();
// If the splat value has been compressed to a bitlength lower
// than the size of the vector lane, we need to re-expand it to
@@ -3210,7 +3210,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
// extension. If it is still the AllOnesValue then this AND is completely
// unneeded.
Constant =
- Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits());
+ Constant.zextOrTrunc(Load->getMemoryVT().getScalarSizeInBits());
bool B;
switch (Load->getExtensionType()) {
@@ -3327,9 +3327,9 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
EVT MemVT = LN0->getMemoryVT();
// If we zero all the possible extended bits, then we can turn this into
// a zextload if we are running before legalize or the operation is legal.
- unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
+ unsigned BitWidth = N1.getValueType().getScalarSizeInBits();
if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
- BitWidth - MemVT.getScalarType().getSizeInBits())) &&
+ BitWidth - MemVT.getScalarSizeInBits())) &&
((!LegalOperations && !LN0->isVolatile()) ||
TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) {
SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
@@ -3347,9 +3347,9 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
EVT MemVT = LN0->getMemoryVT();
// If we zero all the possible extended bits, then we can turn this into
// a zextload if we are running before legalize or the operation is legal.
- unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
+ unsigned BitWidth = N1.getValueType().getScalarSizeInBits();
if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
- BitWidth - MemVT.getScalarType().getSizeInBits())) &&
+ BitWidth - MemVT.getScalarSizeInBits())) &&
((!LegalOperations && !LN0->isVolatile()) ||
TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) {
SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
@@ -3752,13 +3752,13 @@ SDValue DAGCombiner::visitOR(SDNode *N) {
// do not return N0, because undef node may exist in N0
return DAG.getConstant(
APInt::getAllOnesValue(
- N0.getValueType().getScalarType().getSizeInBits()),
+ N0.getValueType().getScalarSizeInBits()),
SDLoc(N), N0.getValueType());
if (ISD::isBuildVectorAllOnes(N1.getNode()))
// do not return N1, because undef node may exist in N1
return DAG.getConstant(
APInt::getAllOnesValue(
- N1.getValueType().getScalarType().getSizeInBits()),
+ N1.getValueType().getScalarSizeInBits()),
SDLoc(N), N1.getValueType());
// fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask)
@@ -4650,7 +4650,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
EVT VT = N0.getValueType();
- unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
+ unsigned OpSizeInBits = VT.getScalarSizeInBits();
// fold vector ops
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
@@ -4802,7 +4802,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
EVT VT = N0.getValueType();
- unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
+ unsigned OpSizeInBits = VT.getScalarSizeInBits();
// fold vector ops
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
@@ -4858,7 +4858,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
uint64_t c2 = N1C->getZExtValue();
EVT InnerShiftVT = N0.getOperand(0).getValueType();
EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
- uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
+ uint64_t InnerShiftSize = InnerShiftVT.getScalarSizeInBits();
// This is only valid if the OpSizeInBits + c1 = size of inner shift.
if (c1 + OpSizeInBits == InnerShiftSize) {
SDLoc DL(N0);
@@ -5712,7 +5712,7 @@ SDValue DAGCombiner::visitVSELECT(SDNode *N) {
EVT VT = LHS.getValueType();
SDValue Shift = DAG.getNode(
ISD::SRA, DL, VT, LHS,
- DAG.getConstant(VT.getScalarType().getSizeInBits() - 1, DL, VT));
+ DAG.getConstant(VT.getScalarSizeInBits() - 1, DL, VT));
SDValue Add = DAG.getNode(ISD::ADD, DL, VT, LHS, Shift);
AddToWorklist(Shift.getNode());
AddToWorklist(Add.getNode());
@@ -5867,7 +5867,7 @@ static SDNode *tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI,
// We can fold this node into a build_vector.
unsigned VTBits = SVT.getSizeInBits();
- unsigned EVTBits = N0->getValueType(0).getScalarType().getSizeInBits();
+ unsigned EVTBits = N0->getValueType(0).getScalarSizeInBits();
SmallVector<SDValue, 8> Elts;
unsigned NumElts = VT.getVectorNumElements();
SDLoc DL(N);
@@ -6102,9 +6102,9 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
// See if the value being truncated is already sign extended. If so, just
// eliminate the trunc/sext pair.
SDValue Op = N0.getOperand(0);
- unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
- unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
- unsigned DestBits = VT.getScalarType().getSizeInBits();
+ unsigned OpBits = Op.getValueType().getScalarSizeInBits();
+ unsigned MidBits = N0.getValueType().getScalarSizeInBits();
+ unsigned DestBits = VT.getScalarSizeInBits();
unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
if (OpBits == DestBits) {
@@ -6592,7 +6592,7 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
// elements we can use a matching integer vector type and then
// truncate/sign extend.
EVT MatchingElementType = EVT::getIntegerVT(
- *DAG.getContext(), N00VT.getScalarType().getSizeInBits());
+ *DAG.getContext(), N00VT.getScalarSizeInBits());
EVT MatchingVectorType = EVT::getVectorVT(
*DAG.getContext(), MatchingElementType, N00VT.getVectorNumElements());
SDValue VsetCC =
@@ -7016,8 +7016,8 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
SDValue N1 = N->getOperand(1);
EVT VT = N->getValueType(0);
EVT EVT = cast<VTSDNode>(N1)->getVT();
- unsigned VTBits = VT.getScalarType().getSizeInBits();
- unsigned EVTBits = EVT.getScalarType().getSizeInBits();
+ unsigned VTBits = VT.getScalarSizeInBits();
+ unsigned EVTBits = EVT.getScalarSizeInBits();
if (N0.isUndef())
return DAG.getUNDEF(VT);
@@ -7041,7 +7041,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
// if x is small enough.
if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
SDValue N00 = N0.getOperand(0);
- if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
+ if (N00.getValueType().getScalarSizeInBits() <= EVTBits &&
(!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00, N1);
}
@@ -12162,8 +12162,8 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
SDValue Shorter =
GetDemandedBits(Value,
APInt::getLowBitsSet(
- Value.getValueType().getScalarType().getSizeInBits(),
- ST->getMemoryVT().getScalarType().getSizeInBits()));
+ Value.getValueType().getScalarSizeInBits(),
+ ST->getMemoryVT().getScalarSizeInBits()));
AddToWorklist(Value.getNode());
if (Shorter.getNode())
return DAG.getTruncStore(Chain, SDLoc(N), Shorter,
@@ -12173,8 +12173,8 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
// SimplifyDemandedBits, which only works if the value has a single use.
if (SimplifyDemandedBits(Value,
APInt::getLowBitsSet(
- Value.getValueType().getScalarType().getSizeInBits(),
- ST->getMemoryVT().getScalarType().getSizeInBits())))
+ Value.getValueType().getScalarSizeInBits(),
+ ST->getMemoryVT().getScalarSizeInBits())))
return SDValue(N, 0);
}
@@ -13459,8 +13459,8 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
// Into:
// indices are equal or bit offsets are equal => V1
// otherwise => (extract_subvec V1, ExtIdx)
- if (InsIdx->getZExtValue() * SmallVT.getScalarType().getSizeInBits() ==
- ExtIdx->getZExtValue() * NVT.getScalarType().getSizeInBits())
+ if (InsIdx->getZExtValue() * SmallVT.getScalarSizeInBits() ==
+ ExtIdx->getZExtValue() * NVT.getScalarSizeInBits())
return DAG.getBitcast(NVT, V->getOperand(1));
return DAG.getNode(
ISD::EXTRACT_SUBVECTOR, dl, NVT,
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