1 files changed, 7 insertions, 12 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp b/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp
index 3b2177c72c4..5c34da0dc55 100644
--- a/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp
@@ -12,6 +12,7 @@
 
 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
+#include "llvm/CodeGen/GlobalISel/Utils.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetRegisterInfo.h"
@@ -39,27 +40,21 @@ bool InstructionSelector::constrainSelectedInstRegOperands(
     DEBUG(dbgs() << "Converting operand: " << MO << '\n');
     assert(MO.isReg() && "Unsupported non-reg operand");
 
+    unsigned Reg = MO.getReg();
     // Physical registers don't need to be constrained.
-    if (TRI.isPhysicalRegister(MO.getReg()))
+    if (TRI.isPhysicalRegister(Reg))
       continue;
 
     // Register operands with a value of 0 (e.g. predicate operands) don't need
     // to be constrained.
-    if (MO.getReg() == 0)
+    if (Reg == 0)
       continue;
 
-    const TargetRegisterClass *RC = TII.getRegClass(I.getDesc(), OpI, &TRI, MF);
-    assert(RC && "Selected inst should have regclass operand");
-
     // If the operand is a vreg, we should constrain its regclass, and only
     // insert COPYs if that's impossible.
-    // If the operand is a physreg, we only insert COPYs if the register class
-    // doesn't contain the register.
-    if (RBI.constrainGenericRegister(MO.getReg(), *RC, MRI))
-      continue;
-
-    DEBUG(dbgs() << "Constraining with COPYs isn't implemented yet");
-    return false;
+    // constrainOperandRegClass does that for us.
+    MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(),
+                                       Reg, OpI));
   }
   return true;
 }