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-rw-r--r--llvm/include/llvm/CodeGen/MachineScheduler.h97
-rw-r--r--llvm/include/llvm/CodeGen/ScheduleDAG.h181
-rw-r--r--llvm/include/llvm/CodeGen/ScheduleDAGMutation.h25
-rw-r--r--llvm/include/llvm/CodeGen/ScheduleDFS.h26
-rw-r--r--llvm/include/llvm/CodeGen/ScheduleHazardRecognizer.h8
-rw-r--r--llvm/include/llvm/CodeGen/ScoreboardHazardRecognizer.h22
-rw-r--r--llvm/include/llvm/CodeGen/StackMaps.h51
-rw-r--r--llvm/include/llvm/CodeGen/StackProtector.h18
8 files changed, 220 insertions, 208 deletions
diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h
index 95f83df3cb9..6b2a16e1d36 100644
--- a/llvm/include/llvm/CodeGen/MachineScheduler.h
+++ b/llvm/include/llvm/CodeGen/MachineScheduler.h
@@ -1,4 +1,4 @@
-//==- MachineScheduler.h - MachineInstr Scheduling Pass ----------*- C++ -*-==//
+//===- MachineScheduler.h - MachineInstr Scheduling Pass --------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -112,12 +112,12 @@ class ScheduleHazardRecognizer;
/// MachineSchedContext provides enough context from the MachineScheduler pass
/// for the target to instantiate a scheduler.
struct MachineSchedContext {
- MachineFunction *MF;
- const MachineLoopInfo *MLI;
- const MachineDominatorTree *MDT;
- const TargetPassConfig *PassConfig;
- AliasAnalysis *AA;
- LiveIntervals *LIS;
+ MachineFunction *MF = nullptr;
+ const MachineLoopInfo *MLI = nullptr;
+ const MachineDominatorTree *MDT = nullptr;
+ const TargetPassConfig *PassConfig = nullptr;
+ AliasAnalysis *AA = nullptr;
+ LiveIntervals *LIS = nullptr;
RegisterClassInfo *RegClassInfo;
@@ -165,22 +165,21 @@ class ScheduleDAGMI;
/// before building the DAG.
struct MachineSchedPolicy {
// Allow the scheduler to disable register pressure tracking.
- bool ShouldTrackPressure;
+ bool ShouldTrackPressure = false;
/// Track LaneMasks to allow reordering of independent subregister writes
/// of the same vreg. \sa MachineSchedStrategy::shouldTrackLaneMasks()
- bool ShouldTrackLaneMasks;
+ bool ShouldTrackLaneMasks = false;
// Allow the scheduler to force top-down or bottom-up scheduling. If neither
// is true, the scheduler runs in both directions and converges.
- bool OnlyTopDown;
- bool OnlyBottomUp;
+ bool OnlyTopDown = false;
+ bool OnlyBottomUp = false;
// Disable heuristic that tries to fetch nodes from long dependency chains
// first.
- bool DisableLatencyHeuristic;
+ bool DisableLatencyHeuristic = false;
- MachineSchedPolicy(): ShouldTrackPressure(false), ShouldTrackLaneMasks(false),
- OnlyTopDown(false), OnlyBottomUp(false), DisableLatencyHeuristic(false) {}
+ MachineSchedPolicy() = default;
};
/// MachineSchedStrategy - Interface to the scheduling algorithm used by
@@ -232,6 +231,7 @@ public:
/// When all predecessor dependencies have been resolved, free this node for
/// top-down scheduling.
virtual void releaseTopNode(SUnit *SU) = 0;
+
/// When all successor dependencies have been resolved, free this node for
/// bottom-up scheduling.
virtual void releaseBottomNode(SUnit *SU) = 0;
@@ -261,24 +261,20 @@ protected:
MachineBasicBlock::iterator CurrentBottom;
/// Record the next node in a scheduled cluster.
- const SUnit *NextClusterPred;
- const SUnit *NextClusterSucc;
+ const SUnit *NextClusterPred = nullptr;
+ const SUnit *NextClusterSucc = nullptr;
#ifndef NDEBUG
/// The number of instructions scheduled so far. Used to cut off the
/// scheduler at the point determined by misched-cutoff.
- unsigned NumInstrsScheduled;
+ unsigned NumInstrsScheduled = 0;
#endif
+
public:
ScheduleDAGMI(MachineSchedContext *C, std::unique_ptr<MachineSchedStrategy> S,
bool RemoveKillFlags)
: ScheduleDAGInstrs(*C->MF, C->MLI, RemoveKillFlags), AA(C->AA),
- LIS(C->LIS), SchedImpl(std::move(S)), Topo(SUnits, &ExitSU),
- NextClusterPred(nullptr), NextClusterSucc(nullptr) {
-#ifndef NDEBUG
- NumInstrsScheduled = 0;
-#endif
- }
+ LIS(C->LIS), SchedImpl(std::move(S)), Topo(SUnits, &ExitSU) {}
// Provide a vtable anchor
~ScheduleDAGMI() override;
@@ -375,7 +371,7 @@ protected:
/// Information about DAG subtrees. If DFSResult is NULL, then SchedulerTrees
/// will be empty.
- SchedDFSResult *DFSResult;
+ SchedDFSResult *DFSResult = nullptr;
BitVector ScheduledTrees;
MachineBasicBlock::iterator LiveRegionEnd;
@@ -389,8 +385,8 @@ protected:
PressureDiffs SUPressureDiffs;
/// Register pressure in this region computed by initRegPressure.
- bool ShouldTrackPressure;
- bool ShouldTrackLaneMasks;
+ bool ShouldTrackPressure = false;
+ bool ShouldTrackLaneMasks = false;
IntervalPressure RegPressure;
RegPressureTracker RPTracker;
@@ -409,16 +405,14 @@ protected:
/// True if disconnected subregister components are already renamed.
/// The renaming is only done on demand if lane masks are tracked.
- bool DisconnectedComponentsRenamed;
+ bool DisconnectedComponentsRenamed = false;
public:
ScheduleDAGMILive(MachineSchedContext *C,
std::unique_ptr<MachineSchedStrategy> S)
: ScheduleDAGMI(C, std::move(S), /*RemoveKillFlags=*/false),
- RegClassInfo(C->RegClassInfo), DFSResult(nullptr),
- ShouldTrackPressure(false), ShouldTrackLaneMasks(false),
- RPTracker(RegPressure), TopRPTracker(TopPressure),
- BotRPTracker(BotPressure), DisconnectedComponentsRenamed(false) {}
+ RegClassInfo(C->RegClassInfo), RPTracker(RegPressure),
+ TopRPTracker(TopPressure), BotRPTracker(BotPressure) {}
~ScheduleDAGMILive() override;
@@ -573,6 +567,8 @@ struct SchedRemainder {
// Unscheduled resources
SmallVector<unsigned, 16> RemainingCounts;
+ SchedRemainder() { reset(); }
+
void reset() {
CriticalPath = 0;
CyclicCritPath = 0;
@@ -581,8 +577,6 @@ struct SchedRemainder {
RemainingCounts.clear();
}
- SchedRemainder() { reset(); }
-
void init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel);
};
@@ -598,14 +592,14 @@ public:
LogMaxQID = 2
};
- ScheduleDAGMI *DAG;
- const TargetSchedModel *SchedModel;
- SchedRemainder *Rem;
+ ScheduleDAGMI *DAG = nullptr;
+ const TargetSchedModel *SchedModel = nullptr;
+ SchedRemainder *Rem = nullptr;
ReadyQueue Available;
ReadyQueue Pending;
- ScheduleHazardRecognizer *HazardRec;
+ ScheduleHazardRecognizer *HazardRec = nullptr;
private:
/// True if the pending Q should be checked/updated before scheduling another
@@ -665,9 +659,7 @@ public:
/// Pending queues extend the ready queues with the same ID and the
/// PendingFlag set.
SchedBoundary(unsigned ID, const Twine &Name):
- DAG(nullptr), SchedModel(nullptr), Rem(nullptr), Available(ID, Name+".A"),
- Pending(ID << LogMaxQID, Name+".P"),
- HazardRec(nullptr) {
+ Available(ID, Name+".A"), Pending(ID << LogMaxQID, Name+".P") {
reset();
}
@@ -781,11 +773,11 @@ public:
/// Policy for scheduling the next instruction in the candidate's zone.
struct CandPolicy {
- bool ReduceLatency;
- unsigned ReduceResIdx;
- unsigned DemandResIdx;
+ bool ReduceLatency = false;
+ unsigned ReduceResIdx = 0;
+ unsigned DemandResIdx = 0;
- CandPolicy(): ReduceLatency(false), ReduceResIdx(0), DemandResIdx(0) {}
+ CandPolicy() = default;
bool operator==(const CandPolicy &RHS) const {
return ReduceLatency == RHS.ReduceLatency &&
@@ -800,12 +792,12 @@ public:
/// Status of an instruction's critical resource consumption.
struct SchedResourceDelta {
// Count critical resources in the scheduled region required by SU.
- unsigned CritResources;
+ unsigned CritResources = 0;
// Count critical resources from another region consumed by SU.
- unsigned DemandedResources;
+ unsigned DemandedResources = 0;
- SchedResourceDelta(): CritResources(0), DemandedResources(0) {}
+ SchedResourceDelta() = default;
bool operator==(const SchedResourceDelta &RHS) const {
return CritResources == RHS.CritResources
@@ -866,13 +858,12 @@ public:
protected:
const MachineSchedContext *Context;
- const TargetSchedModel *SchedModel;
- const TargetRegisterInfo *TRI;
+ const TargetSchedModel *SchedModel = nullptr;
+ const TargetRegisterInfo *TRI = nullptr;
SchedRemainder Rem;
- GenericSchedulerBase(const MachineSchedContext *C):
- Context(C), SchedModel(nullptr), TRI(nullptr) {}
+ GenericSchedulerBase(const MachineSchedContext *C) : Context(C) {}
void setPolicy(CandPolicy &Policy, bool IsPostRA, SchedBoundary &CurrZone,
SchedBoundary *OtherZone);
@@ -887,7 +878,7 @@ protected:
class GenericScheduler : public GenericSchedulerBase {
public:
GenericScheduler(const MachineSchedContext *C):
- GenericSchedulerBase(C), DAG(nullptr), Top(SchedBoundary::TopQID, "TopQ"),
+ GenericSchedulerBase(C), Top(SchedBoundary::TopQID, "TopQ"),
Bot(SchedBoundary::BotQID, "BotQ") {}
void initPolicy(MachineBasicBlock::iterator Begin,
@@ -929,7 +920,7 @@ public:
void registerRoots() override;
protected:
- ScheduleDAGMILive *DAG;
+ ScheduleDAGMILive *DAG = nullptr;
MachineSchedPolicy RegionPolicy;
diff --git a/llvm/include/llvm/CodeGen/ScheduleDAG.h b/llvm/include/llvm/CodeGen/ScheduleDAG.h
index 43b07f9d420..4b9a9f93a5c 100644
--- a/llvm/include/llvm/CodeGen/ScheduleDAG.h
+++ b/llvm/include/llvm/CodeGen/ScheduleDAG.h
@@ -1,4 +1,4 @@
-//===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===//
+//===- llvm/CodeGen/ScheduleDAG.h - Common Base Class -----------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -18,27 +18,32 @@
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/GraphTraits.h"
+#include "llvm/ADT/iterator.h"
#include "llvm/ADT/PointerIntPair.h"
#include "llvm/ADT/SmallVector.h"
-#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Target/TargetLowering.h"
+#include <cassert>
+#include <cstddef>
+#include <iterator>
+#include <string>
+#include <vector>
namespace llvm {
- class SUnit;
- class MachineConstantPool;
- class MachineFunction;
- class MachineRegisterInfo;
- class MachineInstr;
- struct MCSchedClassDesc;
- class TargetRegisterInfo;
- class ScheduleDAG;
- class SDNode;
- class TargetInstrInfo;
- class MCInstrDesc;
- class TargetMachine;
- class TargetRegisterClass;
- template<class Graph> class GraphWriter;
+
+template<class Graph> class GraphWriter;
+class MachineFunction;
+class MachineRegisterInfo;
+class MCInstrDesc;
+struct MCSchedClassDesc;
+class ScheduleDAG;
+class SDNode;
+class SUnit;
+class TargetInstrInfo;
+class TargetMachine;
+class TargetRegisterClass;
+class TargetRegisterInfo;
/// Scheduling dependency. This represents one direction of an edge in the
/// scheduling DAG.
@@ -115,6 +120,7 @@ namespace llvm {
break;
}
}
+
SDep(SUnit *S, OrderKind kind)
: Dep(S, Order), Contents(), Latency(0) {
Contents.OrdKind = kind;
@@ -239,14 +245,15 @@ namespace llvm {
private:
enum : unsigned { BoundaryID = ~0u };
- SDNode *Node; ///< Representative node.
- MachineInstr *Instr; ///< Alternatively, a MachineInstr.
+ SDNode *Node = nullptr; ///< Representative node.
+ MachineInstr *Instr = nullptr; ///< Alternatively, a MachineInstr.
+
public:
- SUnit *OrigNode; ///< If not this, the node from which
- /// this node was cloned.
- /// (SD scheduling only)
+ SUnit *OrigNode = nullptr; ///< If not this, the node from which this node
+ /// was cloned. (SD scheduling only)
- const MCSchedClassDesc *SchedClass; ///< nullptr or resolved SchedClass.
+ const MCSchedClassDesc *SchedClass =
+ nullptr; ///< nullptr or resolved SchedClass.
SmallVector<SDep, 4> Preds; ///< All sunit predecessors.
SmallVector<SDep, 4> Succs; ///< All sunit successors.
@@ -256,92 +263,78 @@ namespace llvm {
typedef SmallVectorImpl<SDep>::const_iterator const_pred_iterator;
typedef SmallVectorImpl<SDep>::const_iterator const_succ_iterator;
- unsigned NodeNum; ///< Entry # of node in the node vector.
- unsigned NodeQueueId; ///< Queue id of node.
- unsigned NumPreds; ///< # of SDep::Data preds.
- unsigned NumSuccs; ///< # of SDep::Data sucss.
- unsigned NumPredsLeft; ///< # of preds not scheduled.
- unsigned NumSuccsLeft; ///< # of succs not scheduled.
- unsigned WeakPredsLeft; ///< # of weak preds not scheduled.
- unsigned WeakSuccsLeft; ///< # of weak succs not scheduled.
- unsigned short NumRegDefsLeft; ///< # of reg defs with no scheduled use.
- unsigned short Latency; ///< Node latency.
- bool isVRegCycle : 1; ///< May use and def the same vreg.
- bool isCall : 1; ///< Is a function call.
- bool isCallOp : 1; ///< Is a function call operand.
- bool isTwoAddress : 1; ///< Is a two-address instruction.
- bool isCommutable : 1; ///< Is a commutable instruction.
- bool hasPhysRegUses : 1; ///< Has physreg uses.
- bool hasPhysRegDefs : 1; ///< Has physreg defs that are being used.
- bool hasPhysRegClobbers : 1; ///< Has any physreg defs, used or not.
- bool isPending : 1; ///< True once pending.
- bool isAvailable : 1; ///< True once available.
- bool isScheduled : 1; ///< True once scheduled.
- bool isScheduleHigh : 1; ///< True if preferable to schedule high.
- bool isScheduleLow : 1; ///< True if preferable to schedule low.
- bool isCloned : 1; ///< True if this node has been cloned.
- bool isUnbuffered : 1; ///< Uses an unbuffered resource.
- bool hasReservedResource : 1; ///< Uses a reserved resource.
- Sched::Preference SchedulingPref; ///< Scheduling preference.
+ unsigned NodeNum = BoundaryID; ///< Entry # of node in the node vector.
+ unsigned NodeQueueId = 0; ///< Queue id of node.
+ unsigned NumPreds = 0; ///< # of SDep::Data preds.
+ unsigned NumSuccs = 0; ///< # of SDep::Data sucss.
+ unsigned NumPredsLeft = 0; ///< # of preds not scheduled.
+ unsigned NumSuccsLeft = 0; ///< # of succs not scheduled.
+ unsigned WeakPredsLeft = 0; ///< # of weak preds not scheduled.
+ unsigned WeakSuccsLeft = 0; ///< # of weak succs not scheduled.
+ unsigned short NumRegDefsLeft = 0; ///< # of reg defs with no scheduled use.
+ unsigned short Latency = 0; ///< Node latency.
+ bool isVRegCycle : 1; ///< May use and def the same vreg.
+ bool isCall : 1; ///< Is a function call.
+ bool isCallOp : 1; ///< Is a function call operand.
+ bool isTwoAddress : 1; ///< Is a two-address instruction.
+ bool isCommutable : 1; ///< Is a commutable instruction.
+ bool hasPhysRegUses : 1; ///< Has physreg uses.
+ bool hasPhysRegDefs : 1; ///< Has physreg defs that are being used.
+ bool hasPhysRegClobbers : 1; ///< Has any physreg defs, used or not.
+ bool isPending : 1; ///< True once pending.
+ bool isAvailable : 1; ///< True once available.
+ bool isScheduled : 1; ///< True once scheduled.
+ bool isScheduleHigh : 1; ///< True if preferable to schedule high.
+ bool isScheduleLow : 1; ///< True if preferable to schedule low.
+ bool isCloned : 1; ///< True if this node has been cloned.
+ bool isUnbuffered : 1; ///< Uses an unbuffered resource.
+ bool hasReservedResource : 1; ///< Uses a reserved resource.
+ Sched::Preference SchedulingPref = Sched::None; ///< Scheduling preference.
private:
- bool isDepthCurrent : 1; ///< True if Depth is current.
- bool isHeightCurrent : 1; ///< True if Height is current.
- unsigned Depth; ///< Node depth.
- unsigned Height; ///< Node height.
+ bool isDepthCurrent : 1; ///< True if Depth is current.
+ bool isHeightCurrent : 1; ///< True if Height is current.
+ unsigned Depth = 0; ///< Node depth.
+ unsigned Height = 0; ///< Node height.
+
public:
- unsigned TopReadyCycle; ///< Cycle relative to start when node is ready.
- unsigned BotReadyCycle; ///< Cycle relative to end when node is ready.
+ unsigned TopReadyCycle = 0; ///< Cycle relative to start when node is ready.
+ unsigned BotReadyCycle = 0; ///< Cycle relative to end when node is ready.
- const TargetRegisterClass *CopyDstRC; ///< Is a special copy node if !=null.
- const TargetRegisterClass *CopySrcRC;
+ const TargetRegisterClass *CopyDstRC =
+ nullptr; ///< Is a special copy node if != nullptr.
+ const TargetRegisterClass *CopySrcRC = nullptr;
/// \brief Constructs an SUnit for pre-regalloc scheduling to represent an
/// SDNode and any nodes flagged to it.
SUnit(SDNode *node, unsigned nodenum)
- : Node(node), Instr(nullptr), OrigNode(nullptr), SchedClass(nullptr),
- NodeNum(nodenum), NodeQueueId(0), NumPreds(0), NumSuccs(0),
- NumPredsLeft(0), NumSuccsLeft(0), WeakPredsLeft(0), WeakSuccsLeft(0),
- NumRegDefsLeft(0), Latency(0), isVRegCycle(false), isCall(false),
+ : Node(node), NodeNum(nodenum), isVRegCycle(false), isCall(false),
isCallOp(false), isTwoAddress(false), isCommutable(false),
hasPhysRegUses(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
isPending(false), isAvailable(false), isScheduled(false),
isScheduleHigh(false), isScheduleLow(false), isCloned(false),
- isUnbuffered(false), hasReservedResource(false),
- SchedulingPref(Sched::None), isDepthCurrent(false),
- isHeightCurrent(false), Depth(0), Height(0), TopReadyCycle(0),
- BotReadyCycle(0), CopyDstRC(nullptr), CopySrcRC(nullptr) {}
+ isUnbuffered(false), hasReservedResource(false), isDepthCurrent(false),
+ isHeightCurrent(false) {}
/// \brief Constructs an SUnit for post-regalloc scheduling to represent a
/// MachineInstr.
SUnit(MachineInstr *instr, unsigned nodenum)
- : Node(nullptr), Instr(instr), OrigNode(nullptr), SchedClass(nullptr),
- NodeNum(nodenum), NodeQueueId(0), NumPreds(0), NumSuccs(0),
- NumPredsLeft(0), NumSuccsLeft(0), WeakPredsLeft(0), WeakSuccsLeft(0),
- NumRegDefsLeft(0), Latency(0), isVRegCycle(false), isCall(false),
+ : Instr(instr), NodeNum(nodenum), isVRegCycle(false), isCall(false),
isCallOp(false), isTwoAddress(false), isCommutable(false),
hasPhysRegUses(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
isPending(false), isAvailable(false), isScheduled(false),
isScheduleHigh(false), isScheduleLow(false), isCloned(false),
- isUnbuffered(false), hasReservedResource(false),
- SchedulingPref(Sched::None), isDepthCurrent(false),
- isHeightCurrent(false), Depth(0), Height(0), TopReadyCycle(0),
- BotReadyCycle(0), CopyDstRC(nullptr), CopySrcRC(nullptr) {}
+ isUnbuffered(false), hasReservedResource(false), isDepthCurrent(false),
+ isHeightCurrent(false) {}
/// \brief Constructs a placeholder SUnit.
SUnit()
- : Node(nullptr), Instr(nullptr), OrigNode(nullptr), SchedClass(nullptr),
- NodeNum(BoundaryID), NodeQueueId(0), NumPreds(0), NumSuccs(0),
- NumPredsLeft(0), NumSuccsLeft(0), WeakPredsLeft(0), WeakSuccsLeft(0),
- NumRegDefsLeft(0), Latency(0), isVRegCycle(false), isCall(false),
- isCallOp(false), isTwoAddress(false), isCommutable(false),
- hasPhysRegUses(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
- isPending(false), isAvailable(false), isScheduled(false),
- isScheduleHigh(false), isScheduleLow(false), isCloned(false),
- isUnbuffered(false), hasReservedResource(false),
- SchedulingPref(Sched::None), isDepthCurrent(false),
- isHeightCurrent(false), Depth(0), Height(0), TopReadyCycle(0),
- BotReadyCycle(0), CopyDstRC(nullptr), CopySrcRC(nullptr) {}
+ : isVRegCycle(false), isCall(false), isCallOp(false), isTwoAddress(false),
+ isCommutable(false), hasPhysRegUses(false), hasPhysRegDefs(false),
+ hasPhysRegClobbers(false), isPending(false), isAvailable(false),
+ isScheduled(false), isScheduleHigh(false), isScheduleLow(false),
+ isCloned(false), isUnbuffered(false), hasReservedResource(false),
+ isDepthCurrent(false), isHeightCurrent(false) {}
/// \brief Boundary nodes are placeholders for the boundary of the
/// scheduling region.
@@ -506,12 +499,14 @@ namespace llvm {
/// decide.
class SchedulingPriorityQueue {
virtual void anchor();
- unsigned CurCycle;
+
+ unsigned CurCycle = 0;
bool HasReadyFilter;
+
public:
- SchedulingPriorityQueue(bool rf = false):
- CurCycle(0), HasReadyFilter(rf) {}
- virtual ~SchedulingPriorityQueue() {}
+ SchedulingPriorityQueue(bool rf = false) : HasReadyFilter(rf) {}
+
+ virtual ~SchedulingPriorityQueue() = default;
virtual bool isBottomUp() const = 0;
@@ -530,6 +525,7 @@ namespace llvm {
assert(!HasReadyFilter && "The ready filter must override isReady()");
return true;
}
+
virtual void push(SUnit *U) = 0;
void push_all(const std::vector<SUnit *> &Nodes) {
@@ -623,6 +619,7 @@ namespace llvm {
unsigned Operand;
SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {}
+
public:
bool operator==(const SUnitIterator& x) const {
return Operand == x.Operand;
@@ -649,6 +646,7 @@ namespace llvm {
unsigned getOperand() const { return Operand; }
const SUnit *getNode() const { return Node; }
+
/// Tests if this is not an SDep::Data dependence.
bool isCtrlDep() const {
return getSDep().isCtrl();
@@ -746,6 +744,7 @@ namespace llvm {
reverse_iterator rend() { return Index2Node.rend(); }
const_reverse_iterator rend() const { return Index2Node.rend(); }
};
-}
-#endif
+} // end namespace llvm
+
+#endif // LLVM_CODEGEN_SCHEDULEDAG_H
diff --git a/llvm/include/llvm/CodeGen/ScheduleDAGMutation.h b/llvm/include/llvm/CodeGen/ScheduleDAGMutation.h
index 02fe2294815..5c236427e0b 100644
--- a/llvm/include/llvm/CodeGen/ScheduleDAGMutation.h
+++ b/llvm/include/llvm/CodeGen/ScheduleDAGMutation.h
@@ -1,4 +1,4 @@
-//==- ScheduleDAGMutation.h - MachineInstr Scheduling ------------*- C++ -*-==//
+//===- ScheduleDAGMutation.h - MachineInstr Scheduling ----------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -16,16 +16,19 @@
#define LLVM_CODEGEN_SCHEDULEDAGMUTATION_H
namespace llvm {
- class ScheduleDAGInstrs;
- /// Mutate the DAG as a postpass after normal DAG building.
- class ScheduleDAGMutation {
- virtual void anchor();
- public:
- virtual ~ScheduleDAGMutation() {}
+class ScheduleDAGInstrs;
- virtual void apply(ScheduleDAGInstrs *DAG) = 0;
- };
-}
+/// Mutate the DAG as a postpass after normal DAG building.
+class ScheduleDAGMutation {
+ virtual void anchor();
-#endif
+public:
+ virtual ~ScheduleDAGMutation() = default;
+
+ virtual void apply(ScheduleDAGInstrs *DAG) = 0;
+};
+
+} // end namespace llvm
+
+#endif // LLVM_CODEGEN_SCHEDULEDAGMUTATION_H
diff --git a/llvm/include/llvm/CodeGen/ScheduleDFS.h b/llvm/include/llvm/CodeGen/ScheduleDFS.h
index b2108ad3bed..c2013661cff 100644
--- a/llvm/include/llvm/CodeGen/ScheduleDFS.h
+++ b/llvm/include/llvm/CodeGen/ScheduleDFS.h
@@ -14,16 +14,16 @@
#ifndef LLVM_CODEGEN_SCHEDULEDFS_H
#define LLVM_CODEGEN_SCHEDULEDFS_H
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/ScheduleDAG.h"
-#include "llvm/Support/DataTypes.h"
#include <vector>
+#include <cassert>
+#include <cstdint>
namespace llvm {
class raw_ostream;
-class IntEqClasses;
-class ScheduleDAGInstrs;
-class SUnit;
/// \brief Represent the ILP of the subDAG rooted at a DAG node.
///
@@ -75,18 +75,18 @@ class SchedDFSResult {
/// interior node. Finally, it is set to a representative subtree ID during
/// finalization.
struct NodeData {
- unsigned InstrCount;
- unsigned SubtreeID;
+ unsigned InstrCount = 0;
+ unsigned SubtreeID = InvalidSubtreeID;
- NodeData(): InstrCount(0), SubtreeID(InvalidSubtreeID) {}
+ NodeData() = default;
};
/// \brief Per-Subtree data computed during DFS.
struct TreeData {
- unsigned ParentTreeID;
- unsigned SubInstrCount;
+ unsigned ParentTreeID = InvalidSubtreeID;
+ unsigned SubInstrCount = 0;
- TreeData(): ParentTreeID(InvalidSubtreeID), SubInstrCount(0) {}
+ TreeData() = default;
};
/// \brief Record a connection between subtrees and the connection level.
@@ -107,7 +107,7 @@ class SchedDFSResult {
// For each subtree discovered during DFS, record its connections to other
// subtrees.
- std::vector<SmallVector<Connection, 4> > SubtreeConnections;
+ std::vector<SmallVector<Connection, 4>> SubtreeConnections;
/// Cache the current connection level of each subtree.
/// This mutable array is updated during scheduling.
@@ -189,6 +189,6 @@ public:
raw_ostream &operator<<(raw_ostream &OS, const ILPValue &Val);
-} // namespace llvm
+} // end namespace llvm
-#endif
+#endif // LLVM_CODEGEN_SCHEDULEDFS_H
diff --git a/llvm/include/llvm/CodeGen/ScheduleHazardRecognizer.h b/llvm/include/llvm/CodeGen/ScheduleHazardRecognizer.h
index 214be2794ba..ace4a2d836c 100644
--- a/llvm/include/llvm/CodeGen/ScheduleHazardRecognizer.h
+++ b/llvm/include/llvm/CodeGen/ScheduleHazardRecognizer.h
@@ -29,10 +29,10 @@ protected:
/// state. Important to restore the state after backtracking. Additionally,
/// MaxLookAhead=0 identifies a fake recognizer, allowing the client to
/// bypass virtual calls. Currently the PostRA scheduler ignores it.
- unsigned MaxLookAhead;
+ unsigned MaxLookAhead = 0;
public:
- ScheduleHazardRecognizer(): MaxLookAhead(0) {}
+ ScheduleHazardRecognizer() = default;
virtual ~ScheduleHazardRecognizer();
enum HazardType {
@@ -117,6 +117,6 @@ public:
}
};
-}
+} // end namespace llvm
-#endif
+#endif // LLVM_CODEGEN_SCHEDULEHAZARDRECOGNIZER_H
diff --git a/llvm/include/llvm/CodeGen/ScoreboardHazardRecognizer.h b/llvm/include/llvm/CodeGen/ScoreboardHazardRecognizer.h
index e0c30fe4d82..466ab532030 100644
--- a/llvm/include/llvm/CodeGen/ScoreboardHazardRecognizer.h
+++ b/llvm/include/llvm/CodeGen/ScoreboardHazardRecognizer.h
@@ -17,8 +17,8 @@
#define LLVM_CODEGEN_SCOREBOARDHAZARDRECOGNIZER_H
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
-#include "llvm/Support/DataTypes.h"
#include <cassert>
+#include <cstddef>
#include <cstring>
namespace llvm {
@@ -38,21 +38,25 @@ class ScoreboardHazardRecognizer : public ScheduleHazardRecognizer {
// bottom-up scheduler, then the scoreboard cycles are the inverse of the
// scheduler's cycles.
class Scoreboard {
- unsigned *Data;
+ unsigned *Data = nullptr;
// The maximum number of cycles monitored by the Scoreboard. This
// value is determined based on the target itineraries to ensure
// that all hazards can be tracked.
- size_t Depth;
+ size_t Depth = 0;
+
// Indices into the Scoreboard that represent the current cycle.
- size_t Head;
+ size_t Head = 0;
+
public:
- Scoreboard():Data(nullptr), Depth(0), Head(0) { }
+ Scoreboard() = default;
+
~Scoreboard() {
delete[] Data;
}
size_t getDepth() const { return Depth; }
+
unsigned& operator[](size_t idx) const {
// Depth is expected to be a power-of-2.
assert(Depth && !(Depth & (Depth - 1)) &&
@@ -93,10 +97,10 @@ class ScoreboardHazardRecognizer : public ScheduleHazardRecognizer {
const ScheduleDAG *DAG;
/// IssueWidth - Max issue per cycle. 0=Unknown.
- unsigned IssueWidth;
+ unsigned IssueWidth = 0;
/// IssueCount - Count instructions issued in this cycle.
- unsigned IssueCount;
+ unsigned IssueCount = 0;
Scoreboard ReservedScoreboard;
Scoreboard RequiredScoreboard;
@@ -119,6 +123,6 @@ public:
void RecedeCycle() override;
};
-}
+} // end namespace llvm
-#endif //!LLVM_CODEGEN_SCOREBOARDHAZARDRECOGNIZER_H
+#endif // LLVM_CODEGEN_SCOREBOARDHAZARDRECOGNIZER_H
diff --git a/llvm/include/llvm/CodeGen/StackMaps.h b/llvm/include/llvm/CodeGen/StackMaps.h
index 7b55b796863..a18936feea7 100644
--- a/llvm/include/llvm/CodeGen/StackMaps.h
+++ b/llvm/include/llvm/CodeGen/StackMaps.h
@@ -1,4 +1,4 @@
-//===------------------- StackMaps.h - StackMaps ----------------*- C++ -*-===//
+//===- StackMaps.h - StackMaps ----------------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -13,7 +13,11 @@
#include "llvm/ADT/MapVector.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/MC/MCSymbol.h"
+#include "llvm/IR/CallingConv.h"
+#include "llvm/Support/Debug.h"
+#include <algorithm>
+#include <cassert>
+#include <cstdint>
#include <vector>
namespace llvm {
@@ -21,6 +25,9 @@ namespace llvm {
class AsmPrinter;
class MCExpr;
class MCStreamer;
+class MCSymbol;
+class raw_ostream;
+class TargetRegisterInfo;
/// \brief MI-level stackmap operands.
///
@@ -189,21 +196,22 @@ public:
Constant,
ConstantIndex
};
- LocationType Type;
- unsigned Size;
- unsigned Reg;
- int64_t Offset;
- Location() : Type(Unprocessed), Size(0), Reg(0), Offset(0) {}
+ LocationType Type = Unprocessed;
+ unsigned Size = 0;
+ unsigned Reg = 0;
+ int64_t Offset = 0;
+
+ Location() = default;
Location(LocationType Type, unsigned Size, unsigned Reg, int64_t Offset)
: Type(Type), Size(Size), Reg(Reg), Offset(Offset) {}
};
struct LiveOutReg {
- unsigned short Reg;
- unsigned short DwarfRegNum;
- unsigned short Size;
+ unsigned short Reg = 0;
+ unsigned short DwarfRegNum = 0;
+ unsigned short Size = 0;
- LiveOutReg() : Reg(0), DwarfRegNum(0), Size(0) {}
+ LiveOutReg() = default;
LiveOutReg(unsigned short Reg, unsigned short DwarfRegNum,
unsigned short Size)
: Reg(Reg), DwarfRegNum(DwarfRegNum), Size(Size) {}
@@ -245,18 +253,20 @@ private:
typedef MapVector<uint64_t, uint64_t> ConstantPool;
struct FunctionInfo {
- uint64_t StackSize;
- uint64_t RecordCount;
- FunctionInfo() : StackSize(0), RecordCount(1) {}
- explicit FunctionInfo(uint64_t StackSize) : StackSize(StackSize), RecordCount(1) {}
+ uint64_t StackSize = 0;
+ uint64_t RecordCount = 1;
+
+ FunctionInfo() = default;
+ explicit FunctionInfo(uint64_t StackSize) : StackSize(StackSize) {}
};
struct CallsiteInfo {
- const MCExpr *CSOffsetExpr;
- uint64_t ID;
+ const MCExpr *CSOffsetExpr = nullptr;
+ uint64_t ID = 0;
LocationVec Locations;
LiveOutVec LiveOuts;
- CallsiteInfo() : CSOffsetExpr(nullptr), ID(0) {}
+
+ CallsiteInfo() = default;
CallsiteInfo(const MCExpr *CSOffsetExpr, uint64_t ID,
LocationVec &&Locations, LiveOutVec &&LiveOuts)
: CSOffsetExpr(CSOffsetExpr), ID(ID), Locations(std::move(Locations)),
@@ -309,6 +319,7 @@ private:
void print(raw_ostream &OS);
void debug() { print(dbgs()); }
};
-}
-#endif
+} // end namespace llvm
+
+#endif // LLVM_CODEGEN_STACKMAPS_H
diff --git a/llvm/include/llvm/CodeGen/StackProtector.h b/llvm/include/llvm/CodeGen/StackProtector.h
index 1b3c0eb4a4d..0655f19a323 100644
--- a/llvm/include/llvm/CodeGen/StackProtector.h
+++ b/llvm/include/llvm/CodeGen/StackProtector.h
@@ -1,4 +1,4 @@
-//===-- StackProtector.h - Stack Protector Insertion ----------------------===//
+//===- StackProtector.h - Stack Protector Insertion -------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -23,8 +23,10 @@
#include "llvm/IR/ValueMap.h"
#include "llvm/Pass.h"
#include "llvm/Target/TargetLowering.h"
+#include "llvm/Target/TargetMachine.h"
namespace llvm {
+
class Function;
class Module;
class PHINode;
@@ -48,11 +50,11 @@ public:
typedef ValueMap<const AllocaInst *, SSPLayoutKind> SSPLayoutMap;
private:
- const TargetMachine *TM;
+ const TargetMachine *TM = nullptr;
/// TLI - Keep a pointer of a TargetLowering to consult for determining
/// target type sizes.
- const TargetLoweringBase *TLI;
+ const TargetLoweringBase *TLI = nullptr;
const Triple Trip;
Function *F;
@@ -67,7 +69,7 @@ private:
/// \brief The minimum size of buffers that will receive stack smashing
/// protection when -fstack-protection is used.
- unsigned SSPBufferSize;
+ unsigned SSPBufferSize = 0;
/// VisitedPHIs - The set of PHI nodes visited when determining
/// if a variable's reference has been taken. This set
@@ -111,12 +113,13 @@ private:
public:
static char ID; // Pass identification, replacement for typeid.
- StackProtector()
- : FunctionPass(ID), TM(nullptr), TLI(nullptr), SSPBufferSize(0) {
+
+ StackProtector() : FunctionPass(ID) {
initializeStackProtectorPass(*PassRegistry::getPassRegistry());
}
+
StackProtector(const TargetMachine *TM)
- : FunctionPass(ID), TM(TM), TLI(nullptr), Trip(TM->getTargetTriple()),
+ : FunctionPass(ID), TM(TM), Trip(TM->getTargetTriple()),
SSPBufferSize(8) {
initializeStackProtectorPass(*PassRegistry::getPassRegistry());
}
@@ -134,6 +137,7 @@ public:
bool runOnFunction(Function &Fn) override;
};
+
} // end namespace llvm
#endif // LLVM_CODEGEN_STACKPROTECTOR_H
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