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-rw-r--r--llvm/include/llvm/CodeGen/MIRYamlMapping.h34
-rw-r--r--llvm/include/llvm/CodeGen/PreISelIntrinsicLowering.h7
-rw-r--r--llvm/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h22
-rw-r--r--llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h16
-rw-r--r--llvm/include/llvm/CodeGen/VirtRegMap.h31
5 files changed, 69 insertions, 41 deletions
diff --git a/llvm/include/llvm/CodeGen/MIRYamlMapping.h b/llvm/include/llvm/CodeGen/MIRYamlMapping.h
index 8e2c6149a82..94578e1d240 100644
--- a/llvm/include/llvm/CodeGen/MIRYamlMapping.h
+++ b/llvm/include/llvm/CodeGen/MIRYamlMapping.h
@@ -12,12 +12,18 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLVM_LIB_CODEGEN_MIRYAMLMAPPING_H
-#define LLVM_LIB_CODEGEN_MIRYAMLMAPPING_H
+#ifndef LLVM_CODEGEN_MIRYAMLMAPPING_H
+#define LLVM_CODEGEN_MIRYAMLMAPPING_H
+#include "llvm/ADT/Optional.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
+#include "llvm/Support/SMLoc.h"
#include "llvm/Support/YAMLTraits.h"
+#include "llvm/Support/raw_ostream.h"
+#include <algorithm>
+#include <cstdint>
+#include <string>
#include <vector>
namespace llvm {
@@ -29,7 +35,7 @@ struct StringValue {
std::string Value;
SMRange SourceRange;
- StringValue() {}
+ StringValue() = default;
StringValue(std::string Value) : Value(std::move(Value)) {}
bool operator==(const StringValue &Other) const {
@@ -38,7 +44,7 @@ struct StringValue {
};
template <> struct ScalarTraits<StringValue> {
- static void output(const StringValue &S, void *, llvm::raw_ostream &OS) {
+ static void output(const StringValue &S, void *, raw_ostream &OS) {
OS << S.Value;
}
@@ -54,12 +60,12 @@ template <> struct ScalarTraits<StringValue> {
};
struct FlowStringValue : StringValue {
- FlowStringValue() {}
+ FlowStringValue() = default;
FlowStringValue(std::string Value) : StringValue(std::move(Value)) {}
};
template <> struct ScalarTraits<FlowStringValue> {
- static void output(const FlowStringValue &S, void *, llvm::raw_ostream &OS) {
+ static void output(const FlowStringValue &S, void *, raw_ostream &OS) {
return ScalarTraits<StringValue>::output(S, nullptr, OS);
}
@@ -72,6 +78,7 @@ template <> struct ScalarTraits<FlowStringValue> {
struct BlockStringValue {
StringValue Value;
+
bool operator==(const BlockStringValue &Other) const {
return Value == Other.Value;
}
@@ -90,10 +97,10 @@ template <> struct BlockScalarTraits<BlockStringValue> {
/// A wrapper around unsigned which contains a source range that's being set
/// during parsing.
struct UnsignedValue {
- unsigned Value;
+ unsigned Value = 0;
SMRange SourceRange;
- UnsignedValue() : Value(0) {}
+ UnsignedValue() = default;
UnsignedValue(unsigned Value) : Value(Value) {}
bool operator==(const UnsignedValue &Other) const {
@@ -148,7 +155,9 @@ struct VirtualRegisterDefinition {
UnsignedValue ID;
StringValue Class;
StringValue PreferredRegister;
+
// TODO: Serialize the target specific register hints.
+
bool operator==(const VirtualRegisterDefinition &Other) const {
return ID == Other.ID && Class == Other.Class &&
PreferredRegister == Other.PreferredRegister;
@@ -169,6 +178,7 @@ template <> struct MappingTraits<VirtualRegisterDefinition> {
struct MachineFunctionLiveIn {
StringValue Register;
StringValue VirtualRegister;
+
bool operator==(const MachineFunctionLiveIn &Other) const {
return Register == Other.Register &&
VirtualRegister == Other.VirtualRegister;
@@ -208,6 +218,7 @@ struct MachineStackObject {
StringValue DebugVar;
StringValue DebugExpr;
StringValue DebugLoc;
+
bool operator==(const MachineStackObject &Other) const {
return ID == Other.ID && Name == Other.Name && Type == Other.Type &&
Offset == Other.Offset && Size == Other.Size &&
@@ -267,6 +278,7 @@ struct FixedMachineStackObject {
bool IsImmutable = false;
bool IsAliased = false;
StringValue CalleeSavedRegister;
+
bool operator==(const FixedMachineStackObject &Other) const {
return ID == Other.ID && Type == Other.Type && Offset == Other.Offset &&
Size == Other.Size && Alignment == Other.Alignment &&
@@ -311,6 +323,7 @@ struct MachineConstantPoolValue {
StringValue Value;
unsigned Alignment = 0;
bool IsTargetSpecific = false;
+
bool operator==(const MachineConstantPoolValue &Other) const {
return ID == Other.ID && Value == Other.Value &&
Alignment == Other.Alignment &&
@@ -331,6 +344,7 @@ struct MachineJumpTable {
struct Entry {
UnsignedValue ID;
std::vector<FlowStringValue> Blocks;
+
bool operator==(const Entry &Other) const {
return ID == Other.ID && Blocks == Other.Blocks;
}
@@ -338,6 +352,7 @@ struct MachineJumpTable {
MachineJumpTableInfo::JTEntryKind Kind = MachineJumpTableInfo::EK_Custom32;
std::vector<Entry> Entries;
+
bool operator==(const MachineJumpTable &Other) const {
return Kind == Other.Kind && Entries == Other.Entries;
}
@@ -396,6 +411,7 @@ struct MachineFrameInfo {
bool HasMustTailInVarArgFunc = false;
StringValue SavePoint;
StringValue RestorePoint;
+
bool operator==(const MachineFrameInfo &Other) const {
return IsFrameAddressTaken == Other.IsFrameAddressTaken &&
IsReturnAddressTaken == Other.IsReturnAddressTaken &&
@@ -494,4 +510,4 @@ template <> struct MappingTraits<MachineFunction> {
} // end namespace yaml
} // end namespace llvm
-#endif
+#endif // LLVM_CODEGEN_MIRYAMLMAPPING_H
diff --git a/llvm/include/llvm/CodeGen/PreISelIntrinsicLowering.h b/llvm/include/llvm/CodeGen/PreISelIntrinsicLowering.h
index 765ca085244..7a007eb8bce 100644
--- a/llvm/include/llvm/CodeGen/PreISelIntrinsicLowering.h
+++ b/llvm/include/llvm/CodeGen/PreISelIntrinsicLowering.h
@@ -1,4 +1,4 @@
-//===--- PreISelIntrinsicLowering.h - Pre-ISel intrinsic lowering pass ----===//
+//===- PreISelIntrinsicLowering.h - Pre-ISel intrinsic lowering pass ------===//
//
// The LLVM Compiler Infrastructure
//
@@ -17,10 +17,13 @@
namespace llvm {
+class Module;
+
struct PreISelIntrinsicLoweringPass
: PassInfoMixin<PreISelIntrinsicLoweringPass> {
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
};
-}
+
+} // end namespace llvm
#endif // LLVM_CODEGEN_PREISELINTRINSICLOWERING_H
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h b/llvm/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h
index 2107e5a3138..18e4c7a83de 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h
@@ -1,5 +1,4 @@
-//===-- llvm/CodeGen/SelectionDAGAddressAnalysis.h ------- DAG Address Analysis
-//---*- C++ -*-===//
+//===- SelectionDAGAddressAnalysis.h - DAG Address Analysis -----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -7,16 +6,17 @@
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
-//
#ifndef LLVM_CODEGEN_SELECTIONDAGADDRESSANALYSIS_H
#define LLVM_CODEGEN_SELECTIONDAGADDRESSANALYSIS_H
-#include "llvm/CodeGen/ISDOpcodes.h"
-#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include <cstdint>
namespace llvm {
+
+class SelectionDAG;
+
/// Helper struct to parse and store a memory address as base + index + offset.
/// We ignore sign extensions when it is safe to do so.
/// The following two expressions are not equivalent. To differentiate we need
@@ -34,12 +34,11 @@ class BaseIndexOffset {
private:
SDValue Base;
SDValue Index;
- int64_t Offset;
- bool IsIndexSignExt;
+ int64_t Offset = 0;
+ bool IsIndexSignExt = false;
public:
- BaseIndexOffset() : Offset(0), IsIndexSignExt(false) {}
-
+ BaseIndexOffset() = default;
BaseIndexOffset(SDValue Base, SDValue Index, int64_t Offset,
bool IsIndexSignExt)
: Base(Base), Index(Index), Offset(Offset),
@@ -59,6 +58,7 @@ public:
/// Parses tree in Ptr for base, index, offset addresses.
static BaseIndexOffset match(SDValue Ptr, const SelectionDAG &DAG);
};
-} // namespace llvm
-#endif
+} // end namespace llvm
+
+#endif // LLVM_CODEGEN_SELECTIONDAGADDRESSANALYSIS_H
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h b/llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h
index ac5092af8de..45c1df48a5e 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h
@@ -1,4 +1,4 @@
-//==-- llvm/CodeGen/SelectionDAGTargetInfo.h - SelectionDAG Info -*- C++ -*-==//
+//==- llvm/CodeGen/SelectionDAGTargetInfo.h - SelectionDAG Info --*- C++ -*-==//
//
// The LLVM Compiler Infrastructure
//
@@ -16,21 +16,24 @@
#ifndef LLVM_CODEGEN_SELECTIONDAGTARGETINFO_H
#define LLVM_CODEGEN_SELECTIONDAGTARGETINFO_H
+#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/Support/CodeGen.h"
+#include <utility>
namespace llvm {
+class SelectionDAG;
+
//===----------------------------------------------------------------------===//
/// Targets can subclass this to parameterize the
/// SelectionDAG lowering and instruction selection process.
///
class SelectionDAGTargetInfo {
- SelectionDAGTargetInfo(const SelectionDAGTargetInfo &) = delete;
- void operator=(const SelectionDAGTargetInfo &) = delete;
-
public:
explicit SelectionDAGTargetInfo() = default;
+ SelectionDAGTargetInfo(const SelectionDAGTargetInfo &) = delete;
+ SelectionDAGTargetInfo &operator=(const SelectionDAGTargetInfo &) = delete;
virtual ~SelectionDAGTargetInfo();
/// Emit target-specific code that performs a memcpy.
@@ -144,6 +147,7 @@ public:
MachinePointerInfo SrcPtrInfo) const {
return std::make_pair(SDValue(), SDValue());
}
+
// Return true when the decision to generate FMA's (or FMS, FMLA etc) rather
// than FMUL and ADD is delegated to the machine combiner.
virtual bool generateFMAsInMachineCombiner(CodeGenOpt::Level OptLevel) const {
@@ -151,6 +155,6 @@ public:
}
};
-} // end llvm namespace
+} // end namespace llvm
-#endif
+#endif // LLVM_CODEGEN_SELECTIONDAGTARGETINFO_H
diff --git a/llvm/include/llvm/CodeGen/VirtRegMap.h b/llvm/include/llvm/CodeGen/VirtRegMap.h
index b9076353fd0..a612b99bf1d 100644
--- a/llvm/include/llvm/CodeGen/VirtRegMap.h
+++ b/llvm/include/llvm/CodeGen/VirtRegMap.h
@@ -1,4 +1,4 @@
-//===-- llvm/CodeGen/VirtRegMap.h - Virtual Register Map -*- C++ -*--------===//
+//===- llvm/CodeGen/VirtRegMap.h - Virtual Register Map ---------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -19,15 +19,17 @@
#include "llvm/ADT/IndexedMap.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/Pass.h"
#include "llvm/Target/TargetRegisterInfo.h"
+#include <cassert>
namespace llvm {
- class MachineInstr;
- class MachineFunction;
- class MachineRegisterInfo;
- class TargetInstrInfo;
- class raw_ostream;
- class SlotIndexes;
+
+class MachineFunction;
+class MachineRegisterInfo;
+class raw_ostream;
+class TargetInstrInfo;
class VirtRegMap : public MachineFunctionPass {
public:
@@ -63,13 +65,14 @@ namespace llvm {
/// createSpillSlot - Allocate a spill slot for RC from MFI.
unsigned createSpillSlot(const TargetRegisterClass *RC);
- VirtRegMap(const VirtRegMap&) = delete;
- void operator=(const VirtRegMap&) = delete;
-
public:
static char ID;
+
VirtRegMap() : MachineFunctionPass(ID), Virt2PhysMap(NO_PHYS_REG),
- Virt2StackSlotMap(NO_STACK_SLOT), Virt2SplitMap(0) { }
+ Virt2StackSlotMap(NO_STACK_SLOT), Virt2SplitMap(0) {}
+ VirtRegMap(const VirtRegMap &) = delete;
+ VirtRegMap &operator=(const VirtRegMap &) = delete;
+
bool runOnMachineFunction(MachineFunction &MF) override;
void getAnalysisUsage(AnalysisUsage &AU) const override {
@@ -166,6 +169,7 @@ namespace llvm {
/// @brief create a mapping for the specifed virtual register to
/// the next available stack slot
int assignVirt2StackSlot(unsigned virtReg);
+
/// @brief create a mapping for the specified virtual register to
/// the specified stack slot
void assignVirt2StackSlot(unsigned virtReg, int frameIndex);
@@ -178,6 +182,7 @@ namespace llvm {
VRM.print(OS);
return OS;
}
-} // End llvm namespace
-#endif
+} // end llvm namespace
+
+#endif // LLVM_CODEGEN_VIRTREGMAP_H
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