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-rw-r--r--llvm/include/llvm/Target/GenericOpcodes.td1
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index e3136b13809..6e6b5820d4b 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -511,6 +511,7 @@ def G_INSERT : Instruction {
let hasSideEffects = 0;
}
+/// Concatenante multiple registers of the same size into a wider register.
def G_MERGE_VALUES : Instruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins variable_ops);
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