diff options
Diffstat (limited to 'lldb/source/Plugins/Instruction')
4 files changed, 222 insertions, 204 deletions
diff --git a/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp b/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp index 702ca061da3..f6c52c0d8be 100644 --- a/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp +++ b/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp @@ -181,21 +181,24 @@ EmulateInstructionARM::GetPluginDescriptionStatic () } EmulateInstruction * -EmulateInstructionARM::CreateInstance (const ArchSpec &arch) +EmulateInstructionARM::CreateInstance (const ArchSpec &arch, InstructionType inst_type) { - if (arch.GetTriple().getArch() == llvm::Triple::arm) - { - std::auto_ptr<EmulateInstructionARM> emulate_insn_ap (new EmulateInstructionARM (arch)); - - if (emulate_insn_ap.get()) - return emulate_insn_ap.release(); - } - else if (arch.GetTriple().getArch() == llvm::Triple::thumb) + if (EmulateInstructionARM::SupportsEmulatingIntructionsOfTypeStatic(inst_type)) { - std::auto_ptr<EmulateInstructionARM> emulate_insn_ap (new EmulateInstructionARM (arch)); - - if (emulate_insn_ap.get()) - return emulate_insn_ap.release(); + if (arch.GetTriple().getArch() == llvm::Triple::arm) + { + std::auto_ptr<EmulateInstructionARM> emulate_insn_ap (new EmulateInstructionARM (arch)); + + if (emulate_insn_ap.get()) + return emulate_insn_ap.release(); + } + else if (arch.GetTriple().getArch() == llvm::Triple::thumb) + { + std::auto_ptr<EmulateInstructionARM> emulate_insn_ap (new EmulateInstructionARM (arch)); + + if (emulate_insn_ap.get()) + return emulate_insn_ap.release(); + } } return NULL; @@ -340,7 +343,7 @@ EmulateInstructionARM::EmulatePUSH (const uint32_t opcode, const ARMEncoding enc Register dwarf_reg; dwarf_reg.SetRegister (eRegisterKindDWARF, 0); Register sp_reg; - sp_reg.SetRegister (eRegisterKindDWARF, dwarf_sp); + sp_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP); for (i=0; i<15; ++i) { if (BitIsSet (registers, i)) @@ -1247,7 +1250,7 @@ EmulateInstructionARM::EmulateADDSPImm (const uint32_t opcode, const ARMEncoding EmulateInstruction::Context context; context.type = EmulateInstruction::eContextAdjustStackPointer; Register sp_reg; - sp_reg.SetRegister (eRegisterKindDWARF, dwarf_sp); + sp_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP); context.SetRegisterPlusOffset (sp_reg, sp_offset); if (d == 15) @@ -1312,7 +1315,7 @@ EmulateInstructionARM::EmulateADDSPRm (const uint32_t opcode, const ARMEncoding EmulateInstruction::Context context; context.type = EmulateInstruction::eContextAddition; Register sp_reg; - sp_reg.SetRegister (eRegisterKindDWARF, dwarf_sp); + sp_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP); Register other_reg; other_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rm); context.SetRegisterRegisterOperands (sp_reg, other_reg); @@ -1849,7 +1852,7 @@ EmulateInstructionARM::EmulateSTRRtSP (const uint32_t opcode, const ARMEncoding EmulateInstruction::Context context; context.type = EmulateInstruction::eContextPushRegisterOnStack; Register sp_reg; - sp_reg.SetRegister (eRegisterKindDWARF, dwarf_sp); + sp_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP); context.SetRegisterPlusOffset (sp_reg, addr - sp); if (Rt != 15) { @@ -1952,7 +1955,7 @@ EmulateInstructionARM::EmulateVPUSH (const uint32_t opcode, const ARMEncoding en Register dwarf_reg; dwarf_reg.SetRegister (eRegisterKindDWARF, 0); Register sp_reg; - sp_reg.SetRegister (eRegisterKindDWARF, dwarf_sp); + sp_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP); for (i=0; i<regs; ++i) { dwarf_reg.num = start_reg + d + i; @@ -2047,7 +2050,7 @@ EmulateInstructionARM::EmulateVPOP (const uint32_t opcode, const ARMEncoding enc Register dwarf_reg; dwarf_reg.SetRegister (eRegisterKindDWARF, 0); Register sp_reg; - sp_reg.SetRegister (eRegisterKindDWARF, dwarf_sp); + sp_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP); for (i=0; i<regs; ++i) { dwarf_reg.num = start_reg + d + i; @@ -9330,7 +9333,7 @@ EmulateInstructionARM::EmulateSUBSPReg (const uint32_t opcode, const ARMEncoding EmulateInstruction::Context context; context.type = eContextSubtraction; Register sp_reg; - sp_reg.SetRegister (eRegisterKindDWARF, dwarf_sp); + sp_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP); Register dwarf_reg; dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m); context.SetRegisterRegisterOperands (sp_reg, dwarf_reg); @@ -10604,7 +10607,7 @@ EmulateInstructionARM::EmulateVLDM (const uint32_t opcode, const ARMEncoding enc // // Combine the word-aligned words in the correct order for current endianness. // D[d+r] = if BigEndian() then word1:word2 else word2:word1; uint64_t data; - if (m_byte_order == eByteOrderBig) + if (GetByteOrder() == eByteOrderBig) { data = word1; data = (data << 32) | word2; @@ -10791,7 +10794,7 @@ EmulateInstructionARM::EmulateVSTM (const uint32_t opcode, const ARMEncoding enc data_reg.num = start_reg + d + r; - if (m_byte_order == eByteOrderBig) + if (GetByteOrder() == eByteOrderBig) { context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - Rn); if (!MemAWrite (context, address, Bits64 (data, 63, 32), addr_byte_size)) @@ -10931,7 +10934,7 @@ EmulateInstructionARM::EmulateVLDR (const uint32_t opcode, ARMEncoding encoding) // // Combine the word-aligned words in the correct order for current endianness. // D[d] = if BigEndian() then word1:word2 else word2:word1; uint64_t data64; - if (m_byte_order == eByteOrderBig) + if (GetByteOrder() == eByteOrderBig) { data64 = word1; data64 = (data64 << 32) | word2; @@ -11059,7 +11062,7 @@ EmulateInstructionARM::EmulateVSTR (const uint32_t opcode, ARMEncoding encoding) if (!success) return false; - if (m_byte_order == eByteOrderBig) + if (GetByteOrder() == eByteOrderBig) { if (!MemAWrite (context, address, Bits64 (data, 63, 32), addr_byte_size)) return false; @@ -12064,7 +12067,7 @@ EmulateInstructionARM::EmulateSUBSPcLrEtc (const uint32_t opcode, const ARMEncod } EmulateInstructionARM::ARMOpcode* -EmulateInstructionARM::GetARMOpcodeForInstruction (const uint32_t opcode) +EmulateInstructionARM::GetARMOpcodeForInstruction (const uint32_t opcode, uint32_t arm_isa) { static ARMOpcode g_arm_opcodes[] = @@ -12289,7 +12292,8 @@ EmulateInstructionARM::GetARMOpcodeForInstruction (const uint32_t opcode) for (size_t i=0; i<k_num_arm_opcodes; ++i) { - if ((g_arm_opcodes[i].mask & opcode) == g_arm_opcodes[i].value) + if ((g_arm_opcodes[i].mask & opcode) == g_arm_opcodes[i].value && + (g_arm_opcodes[i].variants & arm_isa) != 0) return &g_arm_opcodes[i]; } return NULL; @@ -12297,7 +12301,7 @@ EmulateInstructionARM::GetARMOpcodeForInstruction (const uint32_t opcode) EmulateInstructionARM::ARMOpcode* -EmulateInstructionARM::GetThumbOpcodeForInstruction (const uint32_t opcode) +EmulateInstructionARM::GetThumbOpcodeForInstruction (const uint32_t opcode, uint32_t arm_isa) { static ARMOpcode @@ -12607,7 +12611,8 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction (const uint32_t opcode) const size_t k_num_thumb_opcodes = sizeof(g_thumb_opcodes)/sizeof(ARMOpcode); for (size_t i=0; i<k_num_thumb_opcodes; ++i) { - if ((g_thumb_opcodes[i].mask & opcode) == g_thumb_opcodes[i].value) + if ((g_thumb_opcodes[i].mask & opcode) == g_thumb_opcodes[i].value && + (g_thumb_opcodes[i].variants & arm_isa) != 0) return &g_thumb_opcodes[i]; } return NULL; @@ -12636,24 +12641,30 @@ EmulateInstructionARM::SetArchitecture (const ArchSpec &arch) } bool -EmulateInstructionARM::SetInstruction (const Opcode &insn_opcode, const Address &inst_addr) +EmulateInstructionARM::SetInstruction (const Opcode &insn_opcode, const Address &inst_addr, Target *target) { - m_opcode = insn_opcode; + if (EmulateInstruction::SetInstruction (insn_opcode, inst_addr, target)) + { + if (m_arch.GetTriple().getArch() == llvm::Triple::thumb) + m_opcode_mode = eModeThumb; + else + { + AddressClass addr_class = inst_addr.GetAddressClass(); - if (m_arch.GetTriple().getArch() == llvm::Triple::thumb) - m_opcode_mode = eModeThumb; - else - { - AddressClass addr_class = inst_addr.GetAddressClass(); - - if ((addr_class == eAddressClassCode) || (addr_class == eAddressClassUnknown)) - m_opcode_mode = eModeARM; - else if (addr_class == eAddressClassCodeAlternateISA) - m_opcode_mode = eModeThumb; - else - return false; - } - return true; + if ((addr_class == eAddressClassCode) || (addr_class == eAddressClassUnknown)) + m_opcode_mode = eModeARM; + else if (addr_class == eAddressClassCodeAlternateISA) + m_opcode_mode = eModeThumb; + else + return false; + } + if (m_opcode_mode == eModeThumb) + m_opcode_cpsr = CPSR_MODE_USR | MASK_CPSR_T; + else + m_opcode_cpsr = CPSR_MODE_USR; + return true; + } + return false; } bool @@ -12711,6 +12722,12 @@ EmulateInstructionARM::ArchVersion () bool EmulateInstructionARM::ConditionPassed (const uint32_t opcode) { + // If we are ignoring conditions, then always return true. + // this allows us to iterate over disassembly code and still + // emulate an instruction even if we don't have all the right + // bits set in the CPSR register... + if (m_ignore_conditions) + return true; const uint32_t cond = CurrentCond (opcode); @@ -12855,7 +12872,7 @@ EmulateInstructionARM::CurrentModeIsPrivileged () return false; if (mode == 16) - return false; + return false; return true; } @@ -13188,123 +13205,72 @@ EmulateInstructionARM::WriteFlags (Context &context, } bool -EmulateInstructionARM::EvaluateInstruction () +EmulateInstructionARM::EvaluateInstruction (uint32_t evaluate_options) { // Advance the ITSTATE bits to their values for the next instruction. if (m_opcode_mode == eModeThumb && m_it_session.InITBlock()) m_it_session.ITAdvance(); - - ARMOpcode *opcode_data; + ARMOpcode *opcode_data = NULL; if (m_opcode_mode == eModeThumb) - opcode_data = GetThumbOpcodeForInstruction (m_opcode.GetOpcode32()); + opcode_data = GetThumbOpcodeForInstruction (m_opcode.GetOpcode32(), m_arm_isa); else if (m_opcode_mode == eModeARM) - opcode_data = GetARMOpcodeForInstruction (m_opcode.GetOpcode32()); - else - return false; + opcode_data = GetARMOpcodeForInstruction (m_opcode.GetOpcode32(), m_arm_isa); - if (!opcode_data) + if (opcode_data == NULL) return false; - // Verify that we're the right arch for this opcode - switch (m_arm_isa) + const bool auto_advance_pc = evaluate_options & eEmulateInstructionOptionAutoAdvancePC; + m_ignore_conditions = evaluate_options & eEmulateInstructionOptionIgnoreConditions; + + bool success = false; + if (m_opcode_cpsr == 0 || m_ignore_conditions == false) { - case ARMv4: - if (opcode_data->variants != ARMvAll) - return false; - break; - - case ARMv4T: - if ((opcode_data->variants!= ARMvAll) - && (opcode_data->variants != ARMV4T_ABOVE)) - return false; - break; - - case ARMv5T: - case ARMv5TE: - if ((opcode_data->variants != ARMvAll) - && (opcode_data->variants != ARMV4T_ABOVE) - && (opcode_data->variants != ARMV5_ABOVE)) - return false; - break; - - case ARMv5TEJ: - if ((opcode_data->variants != ARMvAll) - && (opcode_data->variants != ARMV4T_ABOVE) - && (opcode_data->variants != ARMV5_ABOVE) - && (opcode_data->variants != ARMV5J_ABOVE)) - return false; - break; - - case ARMv6: - case ARMv6K: - if ((opcode_data->variants != ARMvAll) - && (opcode_data->variants != ARMV4T_ABOVE) - && (opcode_data->variants != ARMV5_ABOVE) - && (opcode_data->variants != ARMV5J_ABOVE) - && (opcode_data->variants != ARMV6_ABOVE)) - return false; - break; - - case ARMv6T2: - case ARMv7: - case ARMv8: - if ((opcode_data->variants != ARMvAll) - && (opcode_data->variants != ARMV4T_ABOVE) - && (opcode_data->variants != ARMV5_ABOVE) - && (opcode_data->variants != ARMV5J_ABOVE) - && (opcode_data->variants != ARMV6_ABOVE) - && (opcode_data->variants != ARMV6T2_ABOVE)) - return false; - break; - - default: -// if (opcode_data->variants != ARMvAll) -// return false; - break; + m_opcode_cpsr = ReadRegisterUnsigned (eRegisterKindDWARF, + dwarf_cpsr, + 0, + &success); } + + // Only return false if we are unable to read the CPSR if we care about conditions + if (success == false && m_ignore_conditions == false) + return false; - // Just for now, for testing purposes. - if (m_baton == NULL) - fprintf (stdout, "\nEvaluateInstruction, opcode (0x%x), found = '%s'\n", m_opcode.GetOpcode32(), - opcode_data->name); - - bool success; - if (m_baton) + uint32_t orig_pc_value = 0; + if (auto_advance_pc) { - uint32_t cpsr_value = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_cpsr, 0, &success); - if (success) - m_opcode_cpsr = cpsr_value; + orig_pc_value = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc, 0, &success); + if (!success) + return false; } - uint32_t orig_pc_value = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc, 0, &success); - if (!success) - return false; - - success = (this->*opcode_data->callback) (m_opcode.GetOpcode32(), opcode_data->encoding); // Call the Emulate... function. - if (!success) - return false; - - uint32_t after_pc_value = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc, 0, &success); + // Call the Emulate... function. + success = (this->*opcode_data->callback) (m_opcode.GetOpcode32(), opcode_data->encoding); if (!success) return false; - if (m_advance_pc && (after_pc_value == orig_pc_value)) + if (auto_advance_pc) { - if (opcode_data->size == eSize32) - after_pc_value += 4; - else if (opcode_data->size == eSize16) - after_pc_value += 2; - - EmulateInstruction::Context context; - context.type = eContextAdvancePC; - context.SetNoArgs(); - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc, after_pc_value)) + uint32_t after_pc_value = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc, 0, &success); + if (!success) return false; + if (auto_advance_pc && (after_pc_value == orig_pc_value)) + { + if (opcode_data->size == eSize32) + after_pc_value += 4; + else if (opcode_data->size == eSize16) + after_pc_value += 2; + + EmulateInstruction::Context context; + context.type = eContextAdvancePC; + context.SetNoArgs(); + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc, after_pc_value)) + return false; + + } } - return true; } @@ -13331,10 +13297,6 @@ EmulateInstructionARM::TestEmulation (Stream *out_stream, ArchSpec &arch, Option } test_opcode = value_sp->GetUInt64Value (); - // If the instruction emulation does not directly update the PC, advance the PC to the next instruction after - // performing the emulation. - SetAdvancePC (true); - if (arch.GetTriple().getArch() == llvm::Triple::arm) { m_opcode_mode = eModeARM; @@ -13392,7 +13354,7 @@ EmulateInstructionARM::TestEmulation (Stream *out_stream, ArchSpec &arch, Option &EmulationStateARM::ReadPseudoRegister, &EmulationStateARM::WritePseudoRegister); - bool success = EvaluateInstruction (); + bool success = EvaluateInstruction (eEmulateInstructionOptionAutoAdvancePC); if (!success) { out_stream->Printf ("TestEmulation: EvaluateInstruction() failed.\n"); @@ -13406,3 +13368,26 @@ EmulateInstructionARM::TestEmulation (Stream *out_stream, ArchSpec &arch, Option return success; } + +const char * +EmulateInstructionARM::GetRegisterName (uint32_t reg_kind, uint32_t reg_num) +{ + if (reg_kind == eRegisterKindGeneric) + { + switch (reg_num) + { + case LLDB_REGNUM_GENERIC_PC: return "pc"; + case LLDB_REGNUM_GENERIC_SP: return "sp"; + case LLDB_REGNUM_GENERIC_FP: return "fp"; + case LLDB_REGNUM_GENERIC_RA: return "lr"; + case LLDB_REGNUM_GENERIC_FLAGS: return "cpsr"; + default: return NULL; + } + } + else if (reg_kind == eRegisterKindDWARF) + { + return GetARMDWARFRegisterName (reg_num); + } + return NULL; +} + diff --git a/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.h b/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.h index faaae730680..bb7b7c23b3b 100644 --- a/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.h +++ b/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.h @@ -75,8 +75,28 @@ public: GetPluginDescriptionStatic (); static lldb_private::EmulateInstruction * - CreateInstance (const lldb_private::ArchSpec &arch); + CreateInstance (const lldb_private::ArchSpec &arch, + InstructionType inst_type); + static bool + SupportsEmulatingIntructionsOfTypeStatic (InstructionType inst_type) + { + switch (inst_type) + { + case eInstructionTypeAny: + case eInstructionTypePrologueEpilogue: + case eInstructionTypePCModifying: + return true; + + case eInstructionTypeAll: + return false; + + default: + break; + } + return false; + } + virtual const char * GetPluginName() { @@ -106,38 +126,43 @@ public: }; EmulateInstructionARM (const ArchSpec &arch) : - EmulateInstruction (lldb::eByteOrderLittle, - 4, - arch), + EmulateInstruction (arch), m_arm_isa (0), m_opcode_mode (eModeInvalid), m_opcode_cpsr (0), - m_it_session () + m_it_session (), + m_ignore_conditions (false) { + SetArchitecture (arch); } - EmulateInstructionARM (const ArchSpec &arch, - void *baton, - ReadMemory read_mem_callback, - WriteMemory write_mem_callback, - ReadRegister read_reg_callback, - WriteRegister write_reg_callback) : - EmulateInstruction (lldb::eByteOrderLittle, // Byte order for ARM - 4, // Address size in byte - arch, - baton, - read_mem_callback, - write_mem_callback, - read_reg_callback, - write_reg_callback), - m_arm_isa (0), - m_opcode_mode (eModeInvalid), - m_opcode_cpsr (0), - m_it_session () +// EmulateInstructionARM (const ArchSpec &arch, +// bool ignore_conditions, +// void *baton, +// ReadMemory read_mem_callback, +// WriteMemory write_mem_callback, +// ReadRegister read_reg_callback, +// WriteRegister write_reg_callback) : +// EmulateInstruction (arch, +// ignore_conditions, +// baton, +// read_mem_callback, +// write_mem_callback, +// read_reg_callback, +// write_reg_callback), +// m_arm_isa (0), +// m_opcode_mode (eModeInvalid), +// m_opcode_cpsr (0), +// m_it_session () +// { +// } + + virtual bool + SupportsEmulatingIntructionsOfType (InstructionType inst_type) { + return SupportsEmulatingIntructionsOfTypeStatic (inst_type); } - - + virtual bool SetArchitecture (const ArchSpec &arch); @@ -145,14 +170,17 @@ public: ReadInstruction (); virtual bool - SetInstruction (const Opcode &insn_opcode, const Address &inst_addr); + SetInstruction (const Opcode &insn_opcode, const Address &inst_addr, Target *target); virtual bool - EvaluateInstruction (); + EvaluateInstruction (uint32_t evaluate_options); virtual bool TestEmulation (Stream *out_stream, ArchSpec &arch, OptionValueDictionary *test_data); + virtual const char * + GetRegisterName (uint32_t reg_kind, uint32_t reg_num); + uint32_t ArchVersion(); @@ -340,10 +368,10 @@ protected: static ARMOpcode* - GetARMOpcodeForInstruction (const uint32_t opcode); + GetARMOpcodeForInstruction (const uint32_t opcode, uint32_t isa_mask); static ARMOpcode* - GetThumbOpcodeForInstruction (const uint32_t opcode); + GetThumbOpcodeForInstruction (const uint32_t opcode, uint32_t isa_mask); // A8.6.123 PUSH bool @@ -948,6 +976,7 @@ protected: uint32_t m_opcode_cpsr; uint32_t m_new_inst_cpsr; // This can get updated by the opcode. ITSession m_it_session; + bool m_ignore_conditions; }; } // namespace lldb_private diff --git a/lldb/source/Plugins/Instruction/ARM/EmulationStateARM.cpp b/lldb/source/Plugins/Instruction/ARM/EmulationStateARM.cpp index 7fb65a495be..72fc484e0d9 100644 --- a/lldb/source/Plugins/Instruction/ARM/EmulationStateARM.cpp +++ b/lldb/source/Plugins/Instruction/ARM/EmulationStateARM.cpp @@ -187,11 +187,12 @@ EmulationStateARM::ReadFromPseudoAddress (lldb::addr_t p_address, uint32_t size, } size_t -EmulationStateARM::ReadPseudoMemory (void *baton, - const EmulateInstruction::Context &context, - lldb::addr_t addr, - void *dst, - size_t length) +EmulationStateARM::ReadPseudoMemory (EmulateInstruction *instruction, + void *baton, + const EmulateInstruction::Context &context, + lldb::addr_t addr, + void *dst, + size_t length) { if (!baton) return 0; @@ -230,11 +231,12 @@ EmulationStateARM::ReadPseudoMemory (void *baton, } size_t -EmulationStateARM::WritePseudoMemory (void *baton, - const EmulateInstruction::Context &context, - lldb::addr_t addr, - const void *dst, - size_t length) +EmulationStateARM::WritePseudoMemory (EmulateInstruction *instruction, + void *baton, + const EmulateInstruction::Context &context, + lldb::addr_t addr, + const void *dst, + size_t length) { if (!baton) return 0; @@ -250,10 +252,11 @@ EmulationStateARM::WritePseudoMemory (void *baton, } bool -EmulationStateARM::ReadPseudoRegister (void *baton, - uint32_t reg_kind, - uint32_t reg_num, - uint64_t ®_value) +EmulationStateARM::ReadPseudoRegister (EmulateInstruction *instruction, + void *baton, + uint32_t reg_kind, + uint32_t reg_num, + uint64_t ®_value) { if (!baton) return false; @@ -284,11 +287,12 @@ EmulationStateARM::ReadPseudoRegister (void *baton, } bool -EmulationStateARM::WritePseudoRegister (void *baton, - const EmulateInstruction::Context &context, - uint32_t reg_kind, - uint32_t reg_num, - uint64_t reg_value) +EmulationStateARM::WritePseudoRegister (EmulateInstruction *instruction, + void *baton, + const EmulateInstruction::Context &context, + uint32_t reg_kind, + uint32_t reg_num, + uint64_t reg_value) { if (!baton) return false; diff --git a/lldb/source/Plugins/Instruction/ARM/EmulationStateARM.h b/lldb/source/Plugins/Instruction/ARM/EmulationStateARM.h index 025ff9e3d94..1dcc680f973 100644 --- a/lldb/source/Plugins/Instruction/ARM/EmulationStateARM.h +++ b/lldb/source/Plugins/Instruction/ARM/EmulationStateARM.h @@ -16,8 +16,6 @@ #include "lldb/Core/Opcode.h" #include "lldb/Interpreter/NamedOptionValue.h" -namespace lldb_private { - class EmulationStateARM { public: @@ -45,37 +43,41 @@ public: ClearPseudoMemory (); bool - LoadPseudoRegistersFromFrame (StackFrame &frame); + LoadPseudoRegistersFromFrame (lldb_private::StackFrame &frame); bool - LoadStateFromDictionary (OptionValueDictionary *test_data); + LoadStateFromDictionary (lldb_private::OptionValueDictionary *test_data); bool CompareState (EmulationStateARM &other_state); static size_t - ReadPseudoMemory (void *baton, - const EmulateInstruction::Context &context, + ReadPseudoMemory (lldb_private::EmulateInstruction *instruction, + void *baton, + const lldb_private::EmulateInstruction::Context &context, lldb::addr_t addr, void *dst, size_t length); static size_t - WritePseudoMemory (void *baton, - const EmulateInstruction::Context &context, + WritePseudoMemory (lldb_private::EmulateInstruction *instruction, + void *baton, + const lldb_private::EmulateInstruction::Context &context, lldb::addr_t addr, const void *dst, size_t length); static bool - ReadPseudoRegister (void *baton, + ReadPseudoRegister (lldb_private::EmulateInstruction *instruction, + void *baton, uint32_t reg_kind, uint32_t reg_num, uint64_t ®_value); static bool - WritePseudoRegister (void *baton, - const EmulateInstruction::Context &context, + WritePseudoRegister (lldb_private::EmulateInstruction *instruction, + void *baton, + const lldb_private::EmulateInstruction::Context &context, uint32_t reg_kind, uint32_t reg_num, uint64_t reg_value); @@ -97,7 +99,5 @@ private: DISALLOW_COPY_AND_ASSIGN (EmulationStateARM); }; - -} // namespace lldb_private #endif // lldb_EmulationStateARM_h_ |
