diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64.td | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrInfo.td | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64Subtarget.h | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SystemOperands.td | 6 | ||||
| -rw-r--r-- | llvm/test/MC/AArch64/armv8.4a-pmu.s | 19 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/AArch64/armv8.4a-pmu.txt | 10 |
6 files changed, 45 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index 51bf35d4a16..5b4c9e2149d 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -285,6 +285,10 @@ def FeatureSEL2 : SubtargetFeature< "sel2", "HasSEL2", "true", "Enable v8.4-A Secure Exception Level 2 extension">; +def FeaturePMU : SubtargetFeature< + "pmu", "HasPMU", "true", + "Enable v8.4-A PMU extension">; + def FeatureTLB_RMI : SubtargetFeature< "tlb-rmi", "HasTLB_RMI", "true", "Enable v8.4-A TLB Range and Maintenance Instructions">; @@ -380,7 +384,7 @@ def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd, FeatureNV, FeatureRASv8_4, FeatureMPAM, FeatureDIT, - FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI, + FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeaturePMU, FeatureTLB_RMI, FeatureFMI, FeatureRCPC_IMMO]>; def HasV8_5aOps : SubtargetFeature< diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 59a1cb25ac6..1981bd5d3bf 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -62,6 +62,9 @@ def HasAM : Predicate<"Subtarget->hasAM()">, def HasSEL2 : Predicate<"Subtarget->hasSEL2()">, AssemblerPredicate<"FeatureSEL2", "sel2">; +def HasPMU : Predicate<"Subtarget->hasPMU()">, + AssemblerPredicate<"FeaturePMU", "pmu">; + def HasTLB_RMI : Predicate<"Subtarget->hasTLB_RMI()">, AssemblerPredicate<"FeatureTLB_RMI", "tlb-rmi">; diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h index 00eb9728468..f3212fae8e5 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.h +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -116,6 +116,7 @@ protected: bool HasTRACEV8_4 = false; bool HasAM = false; bool HasSEL2 = false; + bool HasPMU = false; bool HasTLB_RMI = false; bool HasFMI = false; bool HasRCPC_IMMO = false; @@ -435,6 +436,7 @@ public: bool hasTRACEV8_4() const { return HasTRACEV8_4; } bool hasAM() const { return HasAM; } bool hasSEL2() const { return HasSEL2; } + bool hasPMU() const { return HasPMU; } bool hasTLB_RMI() const { return HasTLB_RMI; } bool hasFMI() const { return HasFMI; } bool hasRCPC_IMMO() const { return HasRCPC_IMMO; } diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td index 2493be41765..05249a4ea6a 100644 --- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td +++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td @@ -1322,6 +1322,12 @@ def : RWSysReg<"CNTHPS_CTL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b001>; def : RWSysReg<"SDER32_EL2", 0b11, 0b100, 0b0001, 0b0011, 0b001>; } // FeatureSEL2 +// v8.4a PMU registers +// Op0 Op1 CRn CRm Op2 +let Requires = [{ {AArch64::FeaturePMU} }] in { +def : RWSysReg<"PMMIR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b110>; +} // FeaturePMU + // v8.4a RAS registers // Op0 Op1 CRn CRm Op2 let Requires = [{ {AArch64::FeatureRASv8_4} }] in { diff --git a/llvm/test/MC/AArch64/armv8.4a-pmu.s b/llvm/test/MC/AArch64/armv8.4a-pmu.s new file mode 100644 index 00000000000..e77a33a7c0f --- /dev/null +++ b/llvm/test/MC/AArch64/armv8.4a-pmu.s @@ -0,0 +1,19 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s \ +// RUN: | FileCheck %s --check-prefix=CHECK + +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +//------------------------------------------------------------------------------ +// ARMV8.4-A PMU +//------------------------------------------------------------------------------ + +// Read/Write registers: + +msr PMMIR_EL1, x0 +mrs x0, PMMIR_EL1 + +//CHECK: msr PMMIR_EL1, x0 // encoding: [0xc0,0x9e,0x18,0xd5] +//CHECK: mrs x0, PMMIR_EL1 // encoding: [0xc0,0x9e,0x38,0xd5] +//CHECK-ERROR: error: expected writable system register or pstate +//CHECK-ERROR: error: expected readable system register diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.4a-pmu.txt b/llvm/test/MC/Disassembler/AArch64/armv8.4a-pmu.txt new file mode 100644 index 00000000000..e61dfda742c --- /dev/null +++ b/llvm/test/MC/Disassembler/AArch64/armv8.4a-pmu.txt @@ -0,0 +1,10 @@ +#RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s +#RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.4a --disassemble < %s | FileCheck %s --check-prefix=CHECK-NOV84 + +[0xc0,0x9e,0x18,0xd5] +[0xc0,0x9e,0x38,0xd5] + +#CHECK: msr PMMIR_EL1, x0 +#CHECK: mrs x0, PMMIR_EL1 +#CHECK-NOV84: msr S3_0_C9_C14_6, x0 +#CHECK-NOV84: mrs x0, S3_0_C9_C14_6 |
