diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/uniform-branch-intrinsic-cond.ll | 27 |
2 files changed, 28 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 21ab9de79c5..3ca39a7c8e5 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -1356,14 +1356,13 @@ SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND, Target = BR->getOperand(1); } - if (Intr->getOpcode() != ISD::INTRINSIC_W_CHAIN) { + if (!isCFIntrinsic(Intr)) { // This is a uniform branch so we don't need to legalize. return BRCOND; } assert(!SetCC || (SetCC->getConstantOperandVal(1) == 1 && - isCFIntrinsic(Intr) && cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == ISD::SETNE)); diff --git a/llvm/test/CodeGen/AMDGPU/uniform-branch-intrinsic-cond.ll b/llvm/test/CodeGen/AMDGPU/uniform-branch-intrinsic-cond.ll new file mode 100644 index 00000000000..93a2c6998be --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/uniform-branch-intrinsic-cond.ll @@ -0,0 +1,27 @@ +; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s + +; This used to raise an assertion due to how the choice between uniform and +; non-uniform branches was determined. +; +; CHECK-LABEL: {{^}}main: +; CHECK: s_cbranch_vccnz +define amdgpu_ps float @main(<4 x i32> inreg %rsrc) { +main_body: + %v = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 0, i1 true, i1 false) + %cc = fcmp une float %v, 1.000000e+00 + br i1 %cc, label %if, label %else + +if: + %u = fadd float %v, %v + br label %else + +else: + %r = phi float [ %v, %main_body ], [ %u, %if ] + ret float %r +} + +; Function Attrs: nounwind readonly +declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #0 + +attributes #0 = { nounwind readonly } |
