diff options
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCMIPeephole.cpp | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir | 5 |
2 files changed, 9 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp index 1b48bbaf1f4..fe4f351e639 100644 --- a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp +++ b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp @@ -1426,6 +1426,12 @@ bool PPCMIPeephole::combineSEXTAndSHL(MachineInstr &MI, if (!MRI->hasOneNonDBGUse(SrcReg)) return false; + assert(SrcMI->getNumOperands() == 2 && "EXTSW should have 2 operands"); + assert(SrcMI->getOperand(1).isReg() && + "EXTSW's second operand should be a register"); + if (!Register::isVirtualRegister(SrcMI->getOperand(1).getReg())) + return false; + LLVM_DEBUG(dbgs() << "Combining pair: "); LLVM_DEBUG(SrcMI->dump()); LLVM_DEBUG(MI.dump()); diff --git a/llvm/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir b/llvm/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir index 5c78e408ffc..76fde05be70 100644 --- a/llvm/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir +++ b/llvm/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir @@ -20,10 +20,11 @@ body: | ; CHECK: B %bb.1 ; CHECK: bb.1: ; CHECK: liveins: $x3 + ; CHECK: [[EXTSW:%[0-9]+]]:g8rc = EXTSW $x3 ; CHECK: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDIo8_]], 2, 61 ; CHECK: $x3 = COPY [[RLDICR]] - ; CHECK: [[EXTSWSLI:%[0-9]+]]:g8rc = EXTSWSLI $x3, 2, implicit-def $carry - ; CHECK: [[ADD8_:%[0-9]+]]:g8rc = ADD8 [[COPY3]], [[EXTSWSLI]] + ; CHECK: [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61 + ; CHECK: [[ADD8_:%[0-9]+]]:g8rc = ADD8 [[COPY3]], [[RLDICR1]] ; CHECK: $x3 = COPY [[ADD8_]] ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit $x3 ; CHECK: bb.2: |
