diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/inline-asm.ll | 13 |
2 files changed, 17 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp index 43cb15f502c..34cd6f704a1 100644 --- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp +++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp @@ -198,6 +198,10 @@ static bool foldVGPRCopyIntoRegSequence(MachineInstr &MI, if (!CopyUse.isCopy()) return false; + // It is illegal to have vreg inputs to a physreg defining reg_sequence. + if (TargetRegisterInfo::isPhysicalRegister(CopyUse.getOperand(0).getReg())) + return false; + const TargetRegisterClass *SrcRC, *DstRC; std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI); diff --git a/llvm/test/CodeGen/AMDGPU/inline-asm.ll b/llvm/test/CodeGen/AMDGPU/inline-asm.ll index 85eb163383e..5d49b11f0d4 100644 --- a/llvm/test/CodeGen/AMDGPU/inline-asm.ll +++ b/llvm/test/CodeGen/AMDGPU/inline-asm.ll @@ -183,3 +183,16 @@ entry: ", ""() ret void } + +; FIXME: Should not have intermediate sgprs +; CHECK-LABEL: {{^}}i64_imm_input_phys_vgpr: +; CHECK: s_mov_b32 s1, 0 +; CHECK: s_mov_b32 s0, 0x1e240 +; CHECK: v_mov_b32_e32 v0, s0 +; CHECK: v_mov_b32_e32 v1, s1 +; CHECK: use v[0:1] +define void @i64_imm_input_phys_vgpr() { +entry: + call void asm sideeffect "; use $0 ", "{VGPR0_VGPR1}"(i64 123456) + ret void +} |
