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-rw-r--r--llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp2
-rw-r--r--llvm/lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp2
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp8
-rw-r--r--llvm/lib/Target/AMDGPU/SIISelLowering.cpp3
-rw-r--r--llvm/lib/Target/AMDGPU/SIInstrInfo.cpp4
-rw-r--r--llvm/lib/Target/Mips/MipsHazardSchedule.cpp4
-rw-r--r--llvm/lib/Target/PowerPC/PPCISelLowering.cpp4
-rw-r--r--llvm/lib/Target/PowerPC/PPCQPXLoadSplat.cpp12
-rw-r--r--llvm/lib/Target/SystemZ/SystemZShortenInst.cpp17
9 files changed, 27 insertions, 29 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
index 37d20793183..2bd655d0aa2 100644
--- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -1682,7 +1682,7 @@ bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB,
// ldrh w2, [x0, #6]
// ; becomes
// str w1, [x0, #4]
- // lsr w2, w1, #16
+ // lsr w2, w1, #16
for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
MBBI != E;) {
MachineInstr *MI = MBBI;
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp
index c2ec90ffda6..19d0ba2e1c4 100644
--- a/llvm/lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp
+++ b/llvm/lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp
@@ -136,7 +136,7 @@ bool AArch64ExternalSymbolizer::tryAddingSymbolicOperand(
else if (ReferenceType ==
LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr) {
CommentStream << "literal pool for: \"";
- CommentStream.write_escaped(ReferenceName);
+ CommentStream.write_escaped(ReferenceName);
CommentStream << "\"";
} else if (ReferenceType ==
LLVMDisassembler_ReferenceType_Out_Objc_CFString_Ref)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index bba92c32195..3c5c188fdc1 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -47,8 +47,7 @@ static bool isCBranchSCC(const SDNode *N) {
if (Cond.getOpcode() == ISD::CopyToReg)
Cond = Cond.getOperand(2);
return Cond.getOpcode() == ISD::SETCC &&
- Cond.getOperand(0).getValueType() == MVT::i32 &&
- Cond.hasOneUse();
+ Cond.getOperand(0).getValueType() == MVT::i32 && Cond.hasOneUse();
}
/// AMDGPU specific code to select AMDGPU machine instructions for
@@ -619,9 +618,8 @@ bool AMDGPUDAGToDAGISel::isGlobalLoad(const MemSDNode *N) const {
return false;
if (N->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS) {
if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
- return !isa<GlobalValue>(
- GetUnderlyingObject(N->getMemOperand()->getValue(),
- CurDAG->getDataLayout()));
+ return !isa<GlobalValue>(GetUnderlyingObject(
+ N->getMemOperand()->getValue(), CurDAG->getDataLayout()));
//TODO: Why do we need this?
if (N->getMemoryVT().bitsLT(MVT::i32))
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 7bbbacdf5a7..7fc94911d13 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -656,8 +656,7 @@ SDValue SITargetLowering::LowerFormalArguments(
// enabled too.
if (CallConv == CallingConv::AMDGPU_PS &&
((Info->getPSInputAddr() & 0x7F) == 0 ||
- ((Info->getPSInputAddr() & 0xF) == 0 &&
- Info->isPSInputAllocated(11)))) {
+ ((Info->getPSInputAddr() & 0xF) == 0 && Info->isPSInputAllocated(11)))) {
CCInfo.AllocateReg(AMDGPU::VGPR0);
CCInfo.AllocateReg(AMDGPU::VGPR1);
Info->markPSInputAllocated(0);
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 850826d74cc..7e64cbe11ee 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -300,8 +300,8 @@ bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
bool SIInstrInfo::shouldClusterMemOps(MachineInstr *FirstLdSt,
MachineInstr *SecondLdSt,
unsigned NumLoads) const {
- const MachineOperand *FirstDst = nullptr;
- const MachineOperand *SecondDst = nullptr;
+ const MachineOperand *FirstDst = nullptr;
+ const MachineOperand *SecondDst = nullptr;
if (isDS(*FirstLdSt) && isDS(*SecondLdSt)) {
FirstDst = getNamedOperand(*FirstLdSt, AMDGPU::OpName::vdst);
diff --git a/llvm/lib/Target/Mips/MipsHazardSchedule.cpp b/llvm/lib/Target/Mips/MipsHazardSchedule.cpp
index edd176548c5..c595c9b46ff 100644
--- a/llvm/lib/Target/Mips/MipsHazardSchedule.cpp
+++ b/llvm/lib/Target/Mips/MipsHazardSchedule.cpp
@@ -23,8 +23,8 @@
///
/// For example:
///
-/// 0x8004 bnec a1,v0,<P+0x18>
-/// 0x8008 beqc a1,a2,<P+0x54>
+/// 0x8004 bnec a1,v0,<P+0x18>
+/// 0x8008 beqc a1,a2,<P+0x54>
///
/// In such cases, the processor is required to signal a Reserved Instruction
/// exception.
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 22ae871dc6b..b9e1a268626 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10588,8 +10588,8 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
MinAlign(LD->getAlignment(), 4), LD->getAAInfo());
if (LD->isIndexed()) {
- // Note that DAGCombine should re-form any pre-increment load(s) from
- // what is produced here if that makes sense.
+ // Note that DAGCombine should re-form any pre-increment load(s) from
+ // what is produced here if that makes sense.
DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), BasePtr);
}
diff --git a/llvm/lib/Target/PowerPC/PPCQPXLoadSplat.cpp b/llvm/lib/Target/PowerPC/PPCQPXLoadSplat.cpp
index 816f05f4bf6..d233cd28a50 100644
--- a/llvm/lib/Target/PowerPC/PPCQPXLoadSplat.cpp
+++ b/llvm/lib/Target/PowerPC/PPCQPXLoadSplat.cpp
@@ -130,12 +130,12 @@ bool PPCQPXLoadSplat::runOnMachineFunction(MachineFunction &MF) {
}
}
- // If this instruction defines the splat register, then we cannot move
- // the previous definition above it. If it reads from the splat
- // register, then it must already be alive from some previous
- // definition, and if the splat register is different from the source
- // register, then this definition must not be the load for which we're
- // searching.
+ // If this instruction defines the splat register, then we cannot move
+ // the previous definition above it. If it reads from the splat
+ // register, then it must already be alive from some previous
+ // definition, and if the splat register is different from the source
+ // register, then this definition must not be the load for which we're
+ // searching.
if (MI->modifiesRegister(SplatReg, TRI) ||
(SrcReg != SplatReg &&
MI->readsRegister(SplatReg, TRI))) {
diff --git a/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp b/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp
index 083718518f2..65bd3f0a214 100644
--- a/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp
@@ -78,12 +78,14 @@ bool SystemZShortenInst::shortenIIF(MachineInstr &MI,
unsigned Reg = MI.getOperand(0).getReg();
// The new opcode will clear the other half of the GR64 reg, so
// cancel if that is live.
- unsigned thisSubRegIdx = (SystemZ::GRH32BitRegClass.contains(Reg) ?
- SystemZ::subreg_h32 : SystemZ::subreg_l32);
- unsigned otherSubRegIdx = (thisSubRegIdx == SystemZ::subreg_l32 ?
- SystemZ::subreg_h32 : SystemZ::subreg_l32);
- unsigned GR64BitReg = TRI->getMatchingSuperReg(Reg, thisSubRegIdx,
- &SystemZ::GR64BitRegClass);
+ unsigned thisSubRegIdx =
+ (SystemZ::GRH32BitRegClass.contains(Reg) ? SystemZ::subreg_h32
+ : SystemZ::subreg_l32);
+ unsigned otherSubRegIdx =
+ (thisSubRegIdx == SystemZ::subreg_l32 ? SystemZ::subreg_h32
+ : SystemZ::subreg_l32);
+ unsigned GR64BitReg =
+ TRI->getMatchingSuperReg(Reg, thisSubRegIdx, &SystemZ::GR64BitRegClass);
unsigned OtherReg = TRI->getSubReg(GR64BitReg, otherSubRegIdx);
if (LiveRegs.contains(OtherReg))
return false;
@@ -139,8 +141,7 @@ bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) {
// Calls shortenOn001 if CCLive is false. CC def operand is added in
// case of success.
-bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI,
- unsigned Opcode) {
+bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI, unsigned Opcode) {
if (!LiveRegs.contains(SystemZ::CC) && shortenOn001(MI, Opcode)) {
MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
.addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead);
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