diff options
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll | 5 |
2 files changed, 11 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index f3288cb0cfa..6e5942fb6ed 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -4681,9 +4681,11 @@ SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch // instruction. unsigned Opc = Cond.getOpcode(); + bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) && + !Subtarget->isThumb1Only(); if (Cond.getResNo() == 1 && (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || - Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) { + Opc == ISD::USUBO || OptimizeMul)) { // Only lower legal XALUO ops. if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0))) return SDValue(); @@ -4730,9 +4732,11 @@ SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch // instruction. unsigned Opc = LHS.getOpcode(); + bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) && + !Subtarget->isThumb1Only(); if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) && (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || - Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO) && + Opc == ISD::USUBO || OptimizeMul) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { // Only lower legal XALUO ops. if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0))) diff --git a/llvm/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll b/llvm/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll index cff5b8998e4..048a1205feb 100644 --- a/llvm/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll +++ b/llvm/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=arm-eabi -mcpu=generic | FileCheck %s +; RUN: llc < %s -mtriple=thumbv6m-eabi | FileCheck %s -check-prefix=CHECK-V6M-THUMB define i32 @sadd(i32 %a, i32 %b) local_unnamed_addr #0 { ; CHECK-LABEL: sadd: @@ -81,6 +82,8 @@ define i32 @smul(i32 %a, i32 %b) local_unnamed_addr #0 { ; CHECK: smull r0, r[[RHI:[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} ; CHECK-NEXT: cmp r[[RHI]], r0, asr #31 ; CHECK-NEXT: moveq pc, lr +; CHECK-V6M-THUMB-LABEL: smul: +; CHECK-V6M-THUMB: bl __aeabi_lmul entry: %0 = tail call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %a, i32 %b) %1 = extractvalue { i32, i1 } %0, 1 @@ -100,6 +103,8 @@ define i32 @umul(i32 %a, i32 %b) local_unnamed_addr #0 { ; CHECK: umull r0, r[[RHI:[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} ; CHECK-NEXT: cmp r[[RHI]], #0 ; CHECK-NEXT: moveq pc, lr +; CHECK-V6M-THUMB-LABEL: umul: +; CHECK-V6M-THUMB: bl __aeabi_lmul entry: %0 = tail call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %a, i32 %b) %1 = extractvalue { i32, i1 } %0, 1 |
