diff options
| -rw-r--r-- | llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp | 24 | ||||
| -rw-r--r-- | llvm/lib/Target/Lanai/LanaiInstrInfo.td | 5 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Lanai/constant_multiply.ll | 8 |
3 files changed, 26 insertions, 11 deletions
diff --git a/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp b/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp index 5aefe869b4c..ed0c99a76ce 100644 --- a/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp +++ b/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp @@ -282,9 +282,29 @@ void LanaiDAGToDAGISel::Select(SDNode *Node) { return; } - // Instruction Selection not handled by the auto-generated - // tablegen selection should be handled here. + // Instruction Selection not handled by the auto-generated tablegen selection + // should be handled here. + EVT VT = Node->getValueType(0); switch (Opcode) { + case ISD::Constant: + if (VT == MVT::i32) { + ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node); + // Materialize zero constants as copies from R0. This allows the coalescer + // to propagate these into other instructions. + if (ConstNode->isNullValue()) { + SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), + SDLoc(Node), Lanai::R0, MVT::i32); + return ReplaceNode(Node, New.getNode()); + } + // Materialize all ones constants as copies from R1. This allows the + // coalescer to propagate these into other instructions. + if (ConstNode->isAllOnesValue()) { + SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), + SDLoc(Node), Lanai::R1, MVT::i32); + return ReplaceNode(Node, New.getNode()); + } + } + break; case ISD::FrameIndex: selectFrameIndex(Node); return; diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.td b/llvm/lib/Target/Lanai/LanaiInstrInfo.td index 02641eaa221..285fca11737 100644 --- a/llvm/lib/Target/Lanai/LanaiInstrInfo.td +++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.td @@ -831,11 +831,6 @@ def TRAILZ : InstSpecial<0b011, (outs GPR:$Rd), (ins GPR:$Rs1), // Non-Instruction Patterns //===----------------------------------------------------------------------===// -// i32 0 and R0 can be used interchangeably. -def : Pat<(i32 0), (i32 R0)>; -// i32 -1 and R1 can be used interchangeably. -def : Pat<(i32 -1), (i32 R1)>; - // unsigned 16-bit immediate def : Pat<(i32 i32lo16z:$imm), (OR_I_LO (i32 R0), imm:$imm)>; diff --git a/llvm/test/CodeGen/Lanai/constant_multiply.ll b/llvm/test/CodeGen/Lanai/constant_multiply.ll index 77c9805e441..80054dbc0f9 100644 --- a/llvm/test/CodeGen/Lanai/constant_multiply.ll +++ b/llvm/test/CodeGen/Lanai/constant_multiply.ll @@ -81,18 +81,18 @@ define i32 @fm8(i32 inreg %a) #0 { } ; CHECK-LABEL: fm9: -; CHECK: sh %r6, 0x3, %r{{[0-9]+}} -; CHECK: sub %r{{[0-9]+}}, %r6, %r{{[0-9]+}} -; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv +; CHECK: sub %r0, %r6, %r{{[0-9]+}} +; CHECK: sh %r6, 0x3, %r9 +; CHECK: sub %r{{[0-9]+}}, %r9, %rv define i32 @fm9(i32 inreg %a) #0 { %1 = mul nsw i32 %a, -9 ret i32 %1 } ; CHECK-LABEL: fm10: -; CHECK: sh %r6, 0x3, %r{{[0-9]+}} ; CHECK: sh %r6, 0x1, %r{{[0-9]+}} ; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}} +; CHECK: sh %r6, 0x3, %r{{[0-9]+}} ; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv define i32 @fm10(i32 inreg %a) #0 { %1 = mul nsw i32 %a, -10 |
