summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--llvm/lib/Target/SystemZ/SystemZFeatures.td1
-rw-r--r--llvm/lib/Target/SystemZ/SystemZISelLowering.cpp21
-rw-r--r--llvm/lib/Target/SystemZ/SystemZISelLowering.h3
-rw-r--r--llvm/lib/Target/SystemZ/SystemZInstrFP.td4
-rw-r--r--llvm/lib/Target/SystemZ/SystemZInstrFormats.td8
-rw-r--r--llvm/lib/Target/SystemZ/SystemZInstrInfo.td11
-rw-r--r--llvm/test/CodeGen/SystemZ/asm-18.ll16
7 files changed, 32 insertions, 32 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZFeatures.td b/llvm/lib/Target/SystemZ/SystemZFeatures.td
index fda9c30fe3f..beff45dba81 100644
--- a/llvm/lib/Target/SystemZ/SystemZFeatures.td
+++ b/llvm/lib/Target/SystemZ/SystemZFeatures.td
@@ -62,6 +62,7 @@ def FeatureLoadStoreOnCond : SystemZFeature<
"load-store-on-cond", "LoadStoreOnCond",
"Assume that the load/store-on-condition facility is installed"
>;
+def FeatureNoLoadStoreOnCond : SystemZMissingFeature<"LoadStoreOnCond">;
def FeaturePopulationCount : SystemZFeature<
"population-count", "PopulationCount",
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index a408a0a2b94..bf5a28cdf4a 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -5954,8 +5954,7 @@ static unsigned forceReg(MachineInstr &MI, MachineOperand &Base,
// Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI.
MachineBasicBlock *
SystemZTargetLowering::emitSelect(MachineInstr &MI,
- MachineBasicBlock *MBB,
- unsigned LOCROpcode) const {
+ MachineBasicBlock *MBB) const {
const SystemZInstrInfo *TII =
static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
@@ -5966,15 +5965,6 @@ SystemZTargetLowering::emitSelect(MachineInstr &MI,
unsigned CCMask = MI.getOperand(4).getImm();
DebugLoc DL = MI.getDebugLoc();
- // Use LOCROpcode if possible.
- if (LOCROpcode && Subtarget.hasLoadStoreOnCond()) {
- BuildMI(*MBB, MI, DL, TII->get(LOCROpcode), DestReg)
- .addReg(FalseReg).addReg(TrueReg)
- .addImm(CCValid).addImm(CCMask);
- MI.eraseFromParent();
- return MBB;
- }
-
MachineBasicBlock *StartMBB = MBB;
MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB);
MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
@@ -6824,18 +6814,15 @@ MachineBasicBlock *SystemZTargetLowering::emitLoadAndTestCmp0(
MachineBasicBlock *SystemZTargetLowering::EmitInstrWithCustomInserter(
MachineInstr &MI, MachineBasicBlock *MBB) const {
switch (MI.getOpcode()) {
- case SystemZ::Select32Mux:
- return emitSelect(MI, MBB,
- Subtarget.hasLoadStoreOnCond2()? SystemZ::LOCRMux : 0);
case SystemZ::Select32:
- return emitSelect(MI, MBB, SystemZ::LOCR);
case SystemZ::Select64:
- return emitSelect(MI, MBB, SystemZ::LOCGR);
case SystemZ::SelectF32:
case SystemZ::SelectF64:
case SystemZ::SelectF128:
+ case SystemZ::SelectVR32:
+ case SystemZ::SelectVR64:
case SystemZ::SelectVR128:
- return emitSelect(MI, MBB, 0);
+ return emitSelect(MI, MBB);
case SystemZ::CondStore8Mux:
return emitCondStore(MI, MBB, SystemZ::STCMux, 0, false);
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.h b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
index dc53d2e3531..c0d19972cdb 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.h
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
@@ -601,8 +601,7 @@ private:
MachineBasicBlock *Target) const;
// Implement EmitInstrWithCustomInserter for individual operation types.
- MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB,
- unsigned LOCROpcode) const;
+ MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB) const;
MachineBasicBlock *emitCondStore(MachineInstr &MI, MachineBasicBlock *BB,
unsigned StoreOpcode, unsigned STOCOpcode,
bool Invert) const;
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFP.td b/llvm/lib/Target/SystemZ/SystemZInstrFP.td
index 6318ebc0d68..4e47752ed12 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFP.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFP.td
@@ -15,6 +15,10 @@
//===----------------------------------------------------------------------===//
// C's ?: operator for floating-point operands.
+let Predicates = [FeatureVector] in {
+ def SelectVR32 : SelectWrapper<f32, VR32>;
+ def SelectVR64 : SelectWrapper<f64, VR64>;
+}
def SelectF32 : SelectWrapper<f32, FP32>;
def SelectF64 : SelectWrapper<f64, FP64>;
let Predicates = [FeatureNoVectorEnhancements1] in
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
index c200479577a..0e63f37bd7e 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -3132,7 +3132,9 @@ class CondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
RegisterOperand cls2>
: InstRRFc<opcode, (outs cls1:$R1),
(ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3),
- mnemonic#"$M3\t$R1, $R2", []> {
+ mnemonic#"$M3\t$R1, $R2",
+ [(set cls1:$R1, (z_select_ccmask cls2:$R2, cls1:$R1src,
+ cond4:$valid, cond4:$M3))]> {
let Constraints = "$R1 = $R1src";
let DisableEncoding = "$R1src";
let CCMaskLast = 1;
@@ -4611,7 +4613,9 @@ class CompareRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
// register.
class CondBinaryRRFPseudo<RegisterOperand cls1, RegisterOperand cls2>
: Pseudo<(outs cls1:$R1),
- (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3), []> {
+ (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3),
+ [(set cls1:$R1, (z_select_ccmask cls2:$R2, cls1:$R1src,
+ cond4:$valid, cond4:$M3))]> {
let Constraints = "$R1 = $R1src";
let DisableEncoding = "$R1src";
let CCMaskLast = 1;
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index 63e8b70dff8..d3ddb64d396 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -325,9 +325,10 @@ let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in {
// Select instructions
//===----------------------------------------------------------------------===//
-def Select32Mux : SelectWrapper<i32, GRX32>, Requires<[FeatureHighWord]>;
-def Select32 : SelectWrapper<i32, GR32>;
-def Select64 : SelectWrapper<i64, GR64>;
+def Select32 : SelectWrapper<i32, GR32>,
+ Requires<[FeatureNoLoadStoreOnCond]>;
+def Select64 : SelectWrapper<i64, GR64>,
+ Requires<[FeatureNoLoadStoreOnCond]>;
// We don't define 32-bit Mux stores if we don't have STOCFH, because the
// low-only STOC should then always be used if possible.
@@ -495,7 +496,7 @@ let Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in {
defm LOCHI : CondBinaryRIEPair<"lochi", 0xEC42, GR32, imm32sx16>;
defm LOCGHI : CondBinaryRIEPair<"locghi", 0xEC46, GR64, imm64sx16>;
- // Move register on condition. Expanded from Select* pseudos and
+ // Move register on condition. Matched via DAG pattern and
// created by early if-conversion.
let isCommutable = 1 in {
// Expands to LOCR or LOCFHR or a branch-and-move sequence,
@@ -530,7 +531,7 @@ let Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in {
}
let Predicates = [FeatureLoadStoreOnCond], Uses = [CC] in {
- // Move register on condition. Expanded from Select* pseudos and
+ // Move register on condition. Matched via DAG pattern and
// created by early if-conversion.
let isCommutable = 1 in {
defm LOCR : CondBinaryRRFPair<"locr", 0xB9F2, GR32, GR32>;
diff --git a/llvm/test/CodeGen/SystemZ/asm-18.ll b/llvm/test/CodeGen/SystemZ/asm-18.ll
index 7909253d188..f7be9b45eb6 100644
--- a/llvm/test/CodeGen/SystemZ/asm-18.ll
+++ b/llvm/test/CodeGen/SystemZ/asm-18.ll
@@ -290,11 +290,14 @@ define void @f12() {
}
; Test selects involving high registers.
+; Note that we prefer to use a LOCR and move the result to a high register.
define void @f13(i32 %x, i32 %y) {
; CHECK-LABEL: f13:
-; CHECK: llihl [[REG:%r[0-5]]], 0
-; CHECK: cije %r2, 0
-; CHECK: iihf [[REG]], 2102030405
+; CHECK-DAG: chi %r2, 0
+; CHECK-DAG: iilf [[REG1:%r[0-5]]], 2102030405
+; CHECK-DAG: lhi [[REG2:%r[0-5]]], 0
+; CHECK: locre [[REG1]], [[REG2]]
+; CHECK: risbhg [[REG:%r[0-5]]], [[REG1]], 0, 159, 32
; CHECK: blah [[REG]]
; CHECK: br %r14
%cmp = icmp eq i32 %x, 0
@@ -306,9 +309,10 @@ define void @f13(i32 %x, i32 %y) {
; Test selects involving low registers.
define void @f14(i32 %x, i32 %y) {
; CHECK-LABEL: f14:
-; CHECK: lhi [[REG:%r[0-5]]], 0
-; CHECK: cije %r2, 0
-; CHECK: iilf [[REG]], 2102030405
+; CHECK-DAG: chi %r2, 0
+; CHECK-DAG: iilf [[REG:%r[0-5]]], 2102030405
+; CHECK-DAG: lhi [[REG1:%r[0-5]]], 0
+; CHECK: locre [[REG]], [[REG1]]
; CHECK: blah [[REG]]
; CHECK: br %r14
%cmp = icmp eq i32 %x, 0
OpenPOWER on IntegriCloud