diff options
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrFormats.td | 4 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/PowerPC/vsx.txt | 6 | ||||
| -rw-r--r-- | llvm/test/MC/PowerPC/vsx.s | 7 |
3 files changed, 15 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td index 0460c64ee43..7091f790da5 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td +++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td @@ -1183,9 +1183,9 @@ class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2, let Inst{11-15} = DCMX{4-0}; let Inst{16-20} = XB{4-0}; let Inst{21-24} = xo1; - let Inst{25} = DCMX{5}; + let Inst{25} = DCMX{6}; let Inst{26-28} = xo2; - let Inst{29} = DCMX{6}; + let Inst{29} = DCMX{5}; let Inst{30} = XB{5}; let Inst{31} = XT{5}; } diff --git a/llvm/test/MC/Disassembler/PowerPC/vsx.txt b/llvm/test/MC/Disassembler/PowerPC/vsx.txt index d431874f605..868716d0614 100644 --- a/llvm/test/MC/Disassembler/PowerPC/vsx.txt +++ b/llvm/test/MC/Disassembler/PowerPC/vsx.txt @@ -853,3 +853,9 @@ # CHECK: mfvsrld 3, 34 0x7c 0x43 0x02 0x67 + +# CHECK: xvtstdcdp 63, 63, 65 +0xf3 0xe1 0xff 0xeb + +# CHECK: xvtstdcsp 63, 63, 34 +0xf3 0xe2 0xfe 0xaf diff --git a/llvm/test/MC/PowerPC/vsx.s b/llvm/test/MC/PowerPC/vsx.s index 0dd9c50b940..73c43961a29 100644 --- a/llvm/test/MC/PowerPC/vsx.s +++ b/llvm/test/MC/PowerPC/vsx.s @@ -948,3 +948,10 @@ # CHECK-BE: mfvsrld 3, 34 # encoding: [0x7c,0x43,0x02,0x67] # CHECK-LE: mfvsrld 3, 34 # encoding: [0x67,0x02,0x43,0x7c] mfvsrld 3, 34 + +# CHECK-BE: xvtstdcdp 63, 63, 65 # encoding: [0xf3,0xe1,0xff,0xeb] +# CHECK-LE: xvtstdcdp 63, 63, 65 # encoding: [0xeb,0xff,0xe1,0xf3] + xvtstdcdp 63, 63, 65 +# CHECK-BE: xvtstdcsp 63, 63, 34 # encoding: [0xf3,0xe2,0xfe,0xaf] +# CHECK-LE: xvtstdcsp 63, 63, 34 # encoding: [0xaf,0xfe,0xe2,0xf3] + xvtstdcsp 63, 63, 34 |
