diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/shrink-carry.mir | 4 |
3 files changed, 8 insertions, 7 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp index 41f989ad322..994658dd3f8 100644 --- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp +++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp @@ -92,7 +92,8 @@ static bool canShrink(MachineInstr &MI, const SIInstrInfo *TII, case AMDGPU::V_ADDC_U32_e64: case AMDGPU::V_SUBB_U32_e64: - if (TII->getNamedOperand(MI, AMDGPU::OpName::src1)->isImm()) + case AMDGPU::V_SUBBREV_U32_e64: + if (!isVGPR(TII->getNamedOperand(MI, AMDGPU::OpName::src1), TRI, MRI)) return false; // Additional verification is needed for sdst/src2. return true; diff --git a/llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll b/llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll index 9e47c7d3449..f94b2fa3aa3 100644 --- a/llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll +++ b/llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll @@ -19,8 +19,8 @@ bb: } ; GCN-LABEL: {{^}}sub1: -; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}} -; GCN: v_subb_u32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, v{{[0-9]+}}, 0, [[CC]] +; GCN: v_cmp_gt_u32_e32 vcc, v{{[0-9]+}}, v{{[0-9]+}} +; GCN: v_subbrev_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc ; GCN-NOT: v_cndmask define amdgpu_kernel void @sub1(i32 addrspace(1)* nocapture %arg) { @@ -134,8 +134,8 @@ bb: } ; GCN-LABEL: {{^}}sext_flclass: -; GCN: v_cmp_class_f32_e{{32|64}} [[CC:[^,]+]], -; GCN: v_subb_u32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, v{{[0-9]+}}, 0, [[CC]] +; GCN: v_cmp_class_f32_e32 vcc, +; GCN: v_subbrev_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc ; GCN-NOT: v_cndmask define amdgpu_kernel void @sext_flclass(i32 addrspace(1)* nocapture %arg, float %x) { diff --git a/llvm/test/CodeGen/AMDGPU/shrink-carry.mir b/llvm/test/CodeGen/AMDGPU/shrink-carry.mir index 8a6c8ceae22..838a4f35626 100644 --- a/llvm/test/CodeGen/AMDGPU/shrink-carry.mir +++ b/llvm/test/CodeGen/AMDGPU/shrink-carry.mir @@ -1,7 +1,7 @@ # RUN: llc -march=amdgcn -verify-machineinstrs -start-before si-shrink-instructions -stop-before si-insert-skips -o - %s | FileCheck -check-prefix=GCN %s # GCN-LABEL: name: subbrev{{$}} -# GCN: V_SUBBREV_U32_e64 0, undef $vgpr0, killed $vcc, implicit $exec +# GCN: V_SUBBREV_U32_e32 0, undef $vgpr0, implicit-def $vcc, implicit killed $vcc, implicit $exec --- name: subbrev @@ -25,7 +25,7 @@ body: | ... # GCN-LABEL: name: subb{{$}} -# GCN: V_SUBB_U32_e64 undef $vgpr0, 0, killed $vcc, implicit $exec +# GCN: V_SUBBREV_U32_e32 0, undef $vgpr0, implicit-def $vcc, implicit killed $vcc, implicit $exec --- name: subb |
