diff options
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/early-if-low8.mir | 27 |
2 files changed, 29 insertions, 0 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp index 0f1b9a4733c..11a042d5096 100644 --- a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp +++ b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp @@ -765,9 +765,11 @@ unsigned HexagonEarlyIfConversion::buildMux(MachineBasicBlock *B, unsigned Opc = 0; switch (DRC->getID()) { case Hexagon::IntRegsRegClassID: + case Hexagon::IntRegsLow8RegClassID: Opc = Hexagon::C2_mux; break; case Hexagon::DoubleRegsRegClassID: + case Hexagon::GeneralDoubleLow8RegsRegClassID: Opc = Hexagon::PS_pselect; break; case Hexagon::HvxVRRegClassID: diff --git a/llvm/test/CodeGen/Hexagon/early-if-low8.mir b/llvm/test/CodeGen/Hexagon/early-if-low8.mir new file mode 100644 index 00000000000..16c6ad26570 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/early-if-low8.mir @@ -0,0 +1,27 @@ +# RUN: llc -march=hexagon -run-pass hexagon-early-if %s -o - | FileCheck %s + +# Make sure that early if-conversion handles the *low8 register classes: +# CHECK: intregslow8 = C2_mux +# CHECK: generaldoublelow8regs = PS_pselect + +--- +name: fred +tracksRegLiveness: true +body: | + bb.0: + liveins: $r0, $r1 + %0:intregslow8 = COPY $r0 + %1:intregslow8 = COPY $r1 + %2:generaldoublelow8regs = A2_tfrpi 1 + %3:predregs = C2_cmpeq %0, %1 + J2_jumpf %3, %bb.2, implicit-def $pc + bb.1: + %4:intregslow8 = A2_addi %0, 1 + %5:generaldoublelow8regs = A2_tfrpi 0 + bb.2: + %6:intregslow8 = PHI %0, %bb.0, %4, %bb.1 + %7:generaldoublelow8regs = PHI %2, %bb.0, %5, %bb.1 + $r0 = COPY %6 + $d1 = COPY %7 + J2_jumpr $r31, implicit $r0, implicit $d1, implicit-def $pc +... |
