diff options
20 files changed, 54 insertions, 58 deletions
diff --git a/llvm/include/llvm/CodeGen/MachineInstrBuilder.h b/llvm/include/llvm/CodeGen/MachineInstrBuilder.h index 641791a7bbb..f19d426a310 100644 --- a/llvm/include/llvm/CodeGen/MachineInstrBuilder.h +++ b/llvm/include/llvm/CodeGen/MachineInstrBuilder.h @@ -447,7 +447,7 @@ public: /// Create an MIBundleBuilder representing an existing instruction or bundle /// that has MI as its head. explicit MIBundleBuilder(MachineInstr *MI) - : MBB(*MI->getParent()), Begin(MI), End(getBundleEnd(MI)) {} + : MBB(*MI->getParent()), Begin(MI), End(getBundleEnd(*MI)) {} /// Return a reference to the basic block containing this bundle. MachineBasicBlock &getMBB() const { return MBB; } diff --git a/llvm/include/llvm/CodeGen/MachineInstrBundle.h b/llvm/include/llvm/CodeGen/MachineInstrBundle.h index 4e88606c05a..9b374cf7991 100644 --- a/llvm/include/llvm/CodeGen/MachineInstrBundle.h +++ b/llvm/include/llvm/CodeGen/MachineInstrBundle.h @@ -43,23 +43,22 @@ bool finalizeBundles(MachineFunction &MF); /// getBundleStart - Returns the first instruction in the bundle containing MI. /// -inline MachineInstr *getBundleStart(MachineInstr *MI) { +inline MachineInstr &getBundleStart(MachineInstr &MI) { MachineBasicBlock::instr_iterator I(MI); while (I->isBundledWithPred()) --I; - return &*I; + return *I; } -inline const MachineInstr *getBundleStart(const MachineInstr *MI) { +inline const MachineInstr &getBundleStart(const MachineInstr &MI) { MachineBasicBlock::const_instr_iterator I(MI); while (I->isBundledWithPred()) --I; - return &*I; + return *I; } /// Return an iterator pointing beyond the bundle containing MI. -inline MachineBasicBlock::instr_iterator -getBundleEnd(MachineInstr *MI) { +inline MachineBasicBlock::instr_iterator getBundleEnd(MachineInstr &MI) { MachineBasicBlock::instr_iterator I(MI); while (I->isBundledWithSucc()) ++I; @@ -68,7 +67,7 @@ getBundleEnd(MachineInstr *MI) { /// Return an iterator pointing beyond the bundle containing MI. inline MachineBasicBlock::const_instr_iterator -getBundleEnd(const MachineInstr *MI) { +getBundleEnd(const MachineInstr &MI) { MachineBasicBlock::const_instr_iterator I(MI); while (I->isBundledWithSucc()) ++I; @@ -114,12 +113,12 @@ protected: /// @param MI The instruction to examine. /// @param WholeBundle When true, visit all operands on the entire bundle. /// - explicit MachineOperandIteratorBase(MachineInstr *MI, bool WholeBundle) { + explicit MachineOperandIteratorBase(MachineInstr &MI, bool WholeBundle) { if (WholeBundle) { - InstrI = getBundleStart(MI)->getIterator(); - InstrE = MI->getParent()->instr_end(); + InstrI = getBundleStart(MI).getIterator(); + InstrE = MI.getParent()->instr_end(); } else { - InstrI = InstrE = MI->getIterator(); + InstrI = InstrE = MI.getIterator(); ++InstrE; } OpI = InstrI->operands_begin(); @@ -216,7 +215,7 @@ public: /// class MIOperands : public MachineOperandIteratorBase { public: - MIOperands(MachineInstr *MI) : MachineOperandIteratorBase(MI, false) {} + MIOperands(MachineInstr &MI) : MachineOperandIteratorBase(MI, false) {} MachineOperand &operator* () const { return deref(); } MachineOperand *operator->() const { return &deref(); } }; @@ -225,8 +224,8 @@ public: /// class ConstMIOperands : public MachineOperandIteratorBase { public: - ConstMIOperands(const MachineInstr *MI) - : MachineOperandIteratorBase(const_cast<MachineInstr*>(MI), false) {} + ConstMIOperands(const MachineInstr &MI) + : MachineOperandIteratorBase(const_cast<MachineInstr &>(MI), false) {} const MachineOperand &operator* () const { return deref(); } const MachineOperand *operator->() const { return &deref(); } }; @@ -236,7 +235,7 @@ public: /// class MIBundleOperands : public MachineOperandIteratorBase { public: - MIBundleOperands(MachineInstr *MI) : MachineOperandIteratorBase(MI, true) {} + MIBundleOperands(MachineInstr &MI) : MachineOperandIteratorBase(MI, true) {} MachineOperand &operator* () const { return deref(); } MachineOperand *operator->() const { return &deref(); } }; @@ -246,8 +245,8 @@ public: /// class ConstMIBundleOperands : public MachineOperandIteratorBase { public: - ConstMIBundleOperands(const MachineInstr *MI) - : MachineOperandIteratorBase(const_cast<MachineInstr*>(MI), true) {} + ConstMIBundleOperands(const MachineInstr &MI) + : MachineOperandIteratorBase(const_cast<MachineInstr &>(MI), true) {} const MachineOperand &operator* () const { return deref(); } const MachineOperand *operator->() const { return &deref(); } }; diff --git a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h index af948324789..65fb1be8c83 100644 --- a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h +++ b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h @@ -835,10 +835,10 @@ public: advance(); } while (Op && Op->getParent() == P); } else if (ByBundle) { - MachineInstr *P = getBundleStart(Op->getParent()); + MachineInstr &P = getBundleStart(*Op->getParent()); do { advance(); - } while (Op && getBundleStart(Op->getParent()) == P); + } while (Op && &getBundleStart(*Op->getParent()) == &P); } return *this; @@ -937,10 +937,10 @@ public: advance(); } while (Op && Op->getParent() == P); } else if (ByBundle) { - MachineInstr *P = getBundleStart(Op->getParent()); + MachineInstr &P = getBundleStart(*Op->getParent()); do { advance(); - } while (Op && getBundleStart(Op->getParent()) == P); + } while (Op && &getBundleStart(*Op->getParent()) == &P); } return *this; @@ -952,15 +952,12 @@ public: // Retrieve a reference to the current operand. MachineInstr &operator*() const { assert(Op && "Cannot dereference end iterator!"); - if (ByBundle) return *(getBundleStart(Op->getParent())); + if (ByBundle) + return getBundleStart(*Op->getParent()); return *Op->getParent(); } - MachineInstr *operator->() const { - assert(Op && "Cannot dereference end iterator!"); - if (ByBundle) return getBundleStart(Op->getParent()); - return Op->getParent(); - } + MachineInstr *operator->() const { return &operator*(); } }; }; diff --git a/llvm/include/llvm/CodeGen/SlotIndexes.h b/llvm/include/llvm/CodeGen/SlotIndexes.h index 907e43b92e9..71af879e142 100644 --- a/llvm/include/llvm/CodeGen/SlotIndexes.h +++ b/llvm/include/llvm/CodeGen/SlotIndexes.h @@ -421,7 +421,7 @@ namespace llvm { /// Returns the base index for the given instruction. SlotIndex getInstructionIndex(const MachineInstr &MI) const { // Instructions inside a bundle have the same number as the bundle itself. - Mi2IndexMap::const_iterator itr = mi2iMap.find(getBundleStart(&MI)); + Mi2IndexMap::const_iterator itr = mi2iMap.find(&getBundleStart(MI)); assert(itr != mi2iMap.end() && "Instruction not found in maps."); return itr->second; } diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index 47f21b36b65..28d793155ce 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -2525,7 +2525,7 @@ isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const { // If we are the operands of one of the branches, this is not a fall // through. Note that targets with delay slots will usually bundle // terminators with the delay slot instruction. - for (ConstMIBundleOperands OP(&MI); OP.isValid(); ++OP) { + for (ConstMIBundleOperands OP(MI); OP.isValid(); ++OP) { if (OP->isJTI()) return false; if (OP->isMBB() && OP->getMBB() == MBB) diff --git a/llvm/lib/CodeGen/IfConversion.cpp b/llvm/lib/CodeGen/IfConversion.cpp index 2bf0c661629..9e898db18f4 100644 --- a/llvm/lib/CodeGen/IfConversion.cpp +++ b/llvm/lib/CodeGen/IfConversion.cpp @@ -1049,7 +1049,7 @@ static void UpdatePredRedefs(MachineInstr &MI, LivePhysRegs &Redefs) { * Remove kill flags from operands with a registers in the @p DontKill set. */ static void RemoveKills(MachineInstr &MI, const LivePhysRegs &DontKill) { - for (MIBundleOperands O(&MI); O.isValid(); ++O) { + for (MIBundleOperands O(MI); O.isValid(); ++O) { if (!O->isReg() || !O->isKill()) continue; if (DontKill.contains(O->getReg())) diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp index 11720b9a204..339c9038188 100644 --- a/llvm/lib/CodeGen/InlineSpiller.cpp +++ b/llvm/lib/CodeGen/InlineSpiller.cpp @@ -855,7 +855,7 @@ bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, // Analyze instruction SmallVector<std::pair<MachineInstr *, unsigned>, 8> Ops; MIBundleOperands::VirtRegInfo RI = - MIBundleOperands(MI).analyzeVirtReg(VirtReg.reg, &Ops); + MIBundleOperands(*MI).analyzeVirtReg(VirtReg.reg, &Ops); if (!RI.Reads) return false; @@ -1121,7 +1121,7 @@ foldMemoryOperand(ArrayRef<std::pair<MachineInstr*, unsigned> > Ops, return false; // Remove LIS for any dead defs in the original MI not in FoldMI. - for (MIBundleOperands MO(MI); MO.isValid(); ++MO) { + for (MIBundleOperands MO(*MI); MO.isValid(); ++MO) { if (!MO->isReg()) continue; unsigned Reg = MO->getReg(); @@ -1133,7 +1133,7 @@ foldMemoryOperand(ArrayRef<std::pair<MachineInstr*, unsigned> > Ops, if (MO->isUse()) continue; MIBundleOperands::PhysRegInfo RI = - MIBundleOperands(FoldMI).analyzePhysReg(Reg, &TRI); + MIBundleOperands(*FoldMI).analyzePhysReg(Reg, &TRI); if (RI.FullyDefined) continue; // FoldMI does not define this physreg. Remove the LI segment. @@ -1248,7 +1248,7 @@ void InlineSpiller::spillAroundUses(unsigned Reg) { // Analyze instruction. SmallVector<std::pair<MachineInstr*, unsigned>, 8> Ops; MIBundleOperands::VirtRegInfo RI = - MIBundleOperands(MI).analyzeVirtReg(Reg, &Ops); + MIBundleOperands(*MI).analyzeVirtReg(Reg, &Ops); // Find the slot index where this instruction reads and writes OldLI. // This is usually the def slot, except for tied early clobbers. diff --git a/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp b/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp index 9b99de75560..27b9ef9c785 100644 --- a/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -1044,7 +1044,7 @@ private: // Kill flags shouldn't be used while live intervals exist, they will be // reinserted by VirtRegRewriter. if (MachineInstr *KillMI = LIS.getInstructionFromIndex(OldIdxIn->end)) - for (MIBundleOperands MO(KillMI); MO.isValid(); ++MO) + for (MIBundleOperands MO(*KillMI); MO.isValid(); ++MO) if (MO->isReg() && MO->isUse()) MO->setIsKill(false); @@ -1380,7 +1380,7 @@ private: return Before; // Check if MII uses Reg. - for (MIBundleOperands MO(MII); MO.isValid(); ++MO) + for (MIBundleOperands MO(*MII); MO.isValid(); ++MO) if (MO->isReg() && TargetRegisterInfo::isPhysicalRegister(MO->getReg()) && TRI.hasRegUnit(MO->getReg(), Reg)) diff --git a/llvm/lib/CodeGen/LivePhysRegs.cpp b/llvm/lib/CodeGen/LivePhysRegs.cpp index 010c33aa377..be8c02c212e 100644 --- a/llvm/lib/CodeGen/LivePhysRegs.cpp +++ b/llvm/lib/CodeGen/LivePhysRegs.cpp @@ -43,7 +43,7 @@ void LivePhysRegs::removeRegsInMask(const MachineOperand &MO, /// Remove Defs, add uses. This is the recommended way of calculating liveness. void LivePhysRegs::stepBackward(const MachineInstr &MI) { // Remove defined registers and regmask kills from the set. - for (ConstMIBundleOperands O(&MI); O.isValid(); ++O) { + for (ConstMIBundleOperands O(MI); O.isValid(); ++O) { if (O->isReg()) { if (!O->isDef()) continue; @@ -56,7 +56,7 @@ void LivePhysRegs::stepBackward(const MachineInstr &MI) { } // Add uses to the set. - for (ConstMIBundleOperands O(&MI); O.isValid(); ++O) { + for (ConstMIBundleOperands O(MI); O.isValid(); ++O) { if (!O->isReg() || !O->readsReg() || O->isUndef()) continue; unsigned Reg = O->getReg(); @@ -73,7 +73,7 @@ void LivePhysRegs::stepBackward(const MachineInstr &MI) { void LivePhysRegs::stepForward(const MachineInstr &MI, SmallVectorImpl<std::pair<unsigned, const MachineOperand*>> &Clobbers) { // Remove killed registers from the set. - for (ConstMIBundleOperands O(&MI); O.isValid(); ++O) { + for (ConstMIBundleOperands O(MI); O.isValid(); ++O) { if (O->isReg()) { unsigned Reg = O->getReg(); if (Reg == 0) diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp index de1f1c71c66..e84595b1232 100644 --- a/llvm/lib/CodeGen/MachineBasicBlock.cpp +++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp @@ -1199,7 +1199,7 @@ MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI, --I; MachineOperandIteratorBase::PhysRegInfo Info = - ConstMIOperands(I).analyzePhysReg(Reg, TRI); + ConstMIOperands(*I).analyzePhysReg(Reg, TRI); // Defs happen after uses so they take precedence if both are present. @@ -1237,7 +1237,7 @@ MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI, if (I != end()) { for (++I; I != end() && N > 0; ++I, --N) { MachineOperandIteratorBase::PhysRegInfo Info = - ConstMIOperands(I).analyzePhysReg(Reg, TRI); + ConstMIOperands(*I).analyzePhysReg(Reg, TRI); // Register is live when we read it here. if (Info.Read) diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp index b1bab6d7302..51335f8d6df 100644 --- a/llvm/lib/CodeGen/MachineInstr.cpp +++ b/llvm/lib/CodeGen/MachineInstr.cpp @@ -1188,7 +1188,7 @@ const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg( // Check every operands inside the bundle if we have // been asked to. if (ExploreBundle) - for (ConstMIBundleOperands OpndIt(this); OpndIt.isValid() && CurRC; + for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC; ++OpndIt) CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl( OpndIt.getOperandNo(), Reg, CurRC, TII, TRI); diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index 8fb8921e94d..15180b52eb1 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -1588,7 +1588,7 @@ void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR, if (Reg != 0) { bool hasDef = false; bool isEarlyClobber = false; - for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) { + for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) { if (!MOI->isReg() || !MOI->isDef()) continue; if (TargetRegisterInfo::isVirtualRegister(Reg)) { @@ -1727,7 +1727,7 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR, // use, or a dead flag on a def. bool hasRead = false; bool hasSubRegDef = false; - for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) { + for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) { if (!MOI->isReg() || MOI->getReg() != Reg) continue; if (LaneMask != 0 && diff --git a/llvm/lib/CodeGen/RegisterPressure.cpp b/llvm/lib/CodeGen/RegisterPressure.cpp index 31ac34b7ade..4ba148ace24 100644 --- a/llvm/lib/CodeGen/RegisterPressure.cpp +++ b/llvm/lib/CodeGen/RegisterPressure.cpp @@ -438,7 +438,7 @@ class RegisterOperandsCollector { TrackLaneMasks(TrackLaneMasks), IgnoreDead(IgnoreDead) {} void collectInstr(const MachineInstr &MI) const { - for (ConstMIBundleOperands OperI(&MI); OperI.isValid(); ++OperI) + for (ConstMIBundleOperands OperI(MI); OperI.isValid(); ++OperI) collectOperand(*OperI); // Remove redundant physreg dead defs. diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp index 66e83f802cc..f63c23f88c5 100644 --- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -1201,7 +1201,7 @@ static void toggleBundleKillFlag(MachineInstr *MI, unsigned Reg, // might set it on too many operands. We will clear as many flags as we // can though. MachineBasicBlock::instr_iterator Begin = MI->getIterator(); - MachineBasicBlock::instr_iterator End = getBundleEnd(MI); + MachineBasicBlock::instr_iterator End = getBundleEnd(*MI); while (Begin != End) { for (MachineOperand &MO : (--End)->operands()) { if (!MO.isReg() || MO.isDef() || Reg != MO.getReg()) @@ -1335,7 +1335,7 @@ void ScheduleDAGInstrs::fixupKills(MachineBasicBlock *MBB) { DEBUG(MI->dump()); DEBUG(if (MI->getOpcode() == TargetOpcode::BUNDLE) { MachineBasicBlock::instr_iterator Begin = MI->getIterator(); - MachineBasicBlock::instr_iterator End = getBundleEnd(MI); + MachineBasicBlock::instr_iterator End = getBundleEnd(*MI); while (++Begin != End) DEBUG(Begin->dump()); }); diff --git a/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp b/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp index 0d9641705ca..90af9404a70 100644 --- a/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp +++ b/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp @@ -351,7 +351,7 @@ MachineInstr *SSACCmpConv::findConvertibleCompare(MachineBasicBlock *MBB) { // Check for flag reads and clobbers. MIOperands::PhysRegInfo PRI = - MIOperands(I).analyzePhysReg(AArch64::NZCV, TRI); + MIOperands(*I).analyzePhysReg(AArch64::NZCV, TRI); if (PRI.Read) { // The ccmp doesn't produce exactly the same flags as the original diff --git a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp index 2a5b87da055..f6d88ef721f 100644 --- a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp +++ b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp @@ -359,7 +359,7 @@ bool HexagonEarlyIfConversion::isValidCandidate(const MachineBasicBlock *B) // update the use of it after predication). PHI uses will be updated // to use a result of a MUX, and a MUX cannot be created for predicate // registers. - for (ConstMIOperands MO(&MI); MO.isValid(); ++MO) { + for (ConstMIOperands MO(MI); MO.isValid(); ++MO) { if (!MO->isReg() || !MO->isDef()) continue; unsigned R = MO->getReg(); @@ -377,7 +377,7 @@ bool HexagonEarlyIfConversion::isValidCandidate(const MachineBasicBlock *B) bool HexagonEarlyIfConversion::usesUndefVReg(const MachineInstr *MI) const { - for (ConstMIOperands MO(MI); MO.isValid(); ++MO) { + for (ConstMIOperands MO(*MI); MO.isValid(); ++MO) { if (!MO->isReg() || !MO->isUse()) continue; unsigned R = MO->getReg(); @@ -456,7 +456,7 @@ unsigned HexagonEarlyIfConversion::countPredicateDefs( const MachineBasicBlock *B) const { unsigned PredDefs = 0; for (auto &MI : *B) { - for (ConstMIOperands MO(&MI); MO.isValid(); ++MO) { + for (ConstMIOperands MO(MI); MO.isValid(); ++MO) { if (!MO->isReg() || !MO->isDef()) continue; unsigned R = MO->getReg(); @@ -721,7 +721,7 @@ void HexagonEarlyIfConversion::predicateInstr(MachineBasicBlock *ToB, assert(COpc); MachineInstrBuilder MIB = BuildMI(*ToB, At, DL, TII->get(COpc)) .addReg(PredR); - for (MIOperands MO(MI); MO.isValid(); ++MO) + for (MIOperands MO(*MI); MO.isValid(); ++MO) MIB.addOperand(*MO); // Set memory references. @@ -980,7 +980,7 @@ void HexagonEarlyIfConversion::replacePhiEdges(MachineBasicBlock *OldB, MachineBasicBlock *SB = *I; MachineBasicBlock::iterator P, N = SB->getFirstNonPHI(); for (P = SB->begin(); P != N; ++P) { - MachineInstr *PN = &*P; + MachineInstr &PN = *P; for (MIOperands MO(PN); MO.isValid(); ++MO) if (MO->isMBB() && MO->getMBB() == OldB) MO->setMBB(NewB); diff --git a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp index 64a2b6cec18..5fa7725fe8a 100644 --- a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp +++ b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp @@ -1446,7 +1446,7 @@ bool HexagonGenInsert::removeDeadCode(MachineDomTreeNode *N) { bool AllDead = true; SmallVector<unsigned,2> Regs; - for (ConstMIOperands Op(MI); Op.isValid(); ++Op) { + for (ConstMIOperands Op(*MI); Op.isValid(); ++Op) { if (!Op->isReg() || !Op->isDef()) continue; unsigned R = Op->getReg(); diff --git a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp index c059d566709..6b5e86bdb88 100644 --- a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp +++ b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp @@ -128,7 +128,7 @@ void HexagonGenMux::getDefsUses(const MachineInstr *MI, BitVector &Defs, expandReg(*R++, Uses); // Look over all operands, and collect explicit defs and uses. - for (ConstMIOperands Mo(MI); Mo.isValid(); ++Mo) { + for (ConstMIOperands Mo(*MI); Mo.isValid(); ++Mo) { if (!Mo->isReg() || Mo->isImplicit()) continue; unsigned R = Mo->getReg(); diff --git a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp index d9675b5173d..e2360181274 100644 --- a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp +++ b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp @@ -332,7 +332,7 @@ bool HexagonGenPredicate::isScalarPred(Register PredReg) { case Hexagon::C4_or_orn: case Hexagon::C2_xor: // Add operands to the queue. - for (ConstMIOperands Mo(DefI); Mo.isValid(); ++Mo) + for (ConstMIOperands Mo(*DefI); Mo.isValid(); ++Mo) if (Mo->isReg() && Mo->isUse()) WorkQ.push(Register(Mo->getReg())); break; diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index 9ca5d85f42e..1bf6c7259d5 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -4070,7 +4070,7 @@ unsigned HexagonInstrInfo::nonDbgBundleSize( assert(BundleHead->isBundle() && "Not a bundle header"); auto MII = BundleHead.getInstrIterator(); // Skip the bundle header. - return nonDbgMICount(++MII, getBundleEnd(BundleHead)); + return nonDbgMICount(++MII, getBundleEnd(*BundleHead)); } |
