diff options
22 files changed, 124 insertions, 38 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td index dd30e20a743..eac024a489c 100644 --- a/llvm/lib/Target/Mips/MipsInstrFPU.td +++ b/llvm/lib/Target/Mips/MipsInstrFPU.td @@ -130,6 +130,15 @@ class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, HARDFLOAT, NeverHasSideEffects; +class CVT_PS_S_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, InstrItinClass Itin, bit IsComm, + SDPatternOperator OpNode= null_frag> : + InstSE<(outs DstRC:$fd), (ins SrcRC:$fs, SrcRC:$ft), + !strconcat(opstr, "\t$fd, $fs, $ft"), + [(set DstRC:$fd, (OpNode SrcRC:$fs, SrcRC:$ft))], Itin, FrmFR, opstr>, + HARDFLOAT { + let isCommutable = IsComm; +} + multiclass ABSS_M<string opstr, InstrItinClass Itin, SDPatternOperator OpNode= null_frag> { def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>, @@ -432,6 +441,29 @@ let AdditionalPredicates = [NotInMicroMips] in { def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_32; } + +let DecoderNamespace = "MipsFP64" in { + let AdditionalPredicates = [NotInMicroMips] in { + def PLL_PS64 : ADDS_FT<"pll.ps", FGR64Opnd, II_CVT, 0>, + ADDS_FM<0x2C, 22>, + ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; + def PLU_PS64 : ADDS_FT<"plu.ps", FGR64Opnd, II_CVT, 0>, + ADDS_FM<0x2D, 22>, + ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; + + def CVT_S_PU64 : ABSS_FT<"cvt.s.pu", FGR32Opnd, FGR64Opnd, II_CVT>, + ABSS_FM<0x20, 22>, + ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; + def CVT_S_PL64 : ABSS_FT<"cvt.s.pl", FGR32Opnd, FGR64Opnd, II_CVT>, + ABSS_FM<0x28, 22>, + ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; + + def CVT_PS_S64 : CVT_PS_S_FT<"cvt.ps.s", FGR64Opnd, FGR32Opnd, II_CVT, 0>, + ADDS_FM<0x26, 16>, + ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; + } +} + let DecoderNamespace = "MipsFP64" in { let AdditionalPredicates = [NotInMicroMips] in { def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>, diff --git a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64-el.txt b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64-el.txt index d1abea5801b..2eba5f5667a 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64-el.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64-el.txt @@ -15,5 +15,12 @@ 0x21 0x10 0x00 0x46 # CHECK: cvt.d.s $f0, $f2 0x21 0x10 0x80 0x46 # CHECK: cvt.d.w $f0, $f2 0x20 0x10 0x20 0x46 # CHECK: cvt.s.d $f0, $f2 +0x21 0x81 0xa0 0x46 # CHECK: cvt.d.l $f4, $f16 +0xe0 0xf3 0xa0 0x46 # CHECK: cvt.s.l $f15, $f30 +0xa0 0xd3 0xc0 0x46 # CHECK: cvt.s.pu $f14, $f26 +0xa6 0x90 0x14 0x46 # CHECK: cvt.ps.s $f2, $f18, $f20 +0xa8 0x17 0xc0 0x46 # CHECK: cvt.s.pl $f30, $f2 +0x2c 0x46 0xde 0x46 # CHECK: pll.ps $f24, $f8, $f30 +0x2d 0xd0 0xdc 0x46 # CHECK: plu.ps $f0, $f26, $f28 0x00 0x00 0xe4 0x44 # CHECK: mthc1 $4, $f0 0x00 0x00 0x64 0x44 # CHECK: mfhc1 $4, $f0 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64.txt b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64.txt index e784e526d63..c47219abc23 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64.txt @@ -15,5 +15,12 @@ 0x46 0x00 0x10 0x21 # CHECK: cvt.d.s $f0, $f2 0x46 0x80 0x10 0x21 # CHECK: cvt.d.w $f0, $f2 0x46 0x20 0x10 0x20 # CHECK: cvt.s.d $f0, $f2 +0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16 +0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30 +0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26 +0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20 +0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2 +0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30 +0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28 0x44 0xe4 0x00 0x00 # CHECK: mthc1 $4, $f0 0x44 0x64 0x00 0x00 # CHECK: mfhc1 $4, $f0 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64-el.txt b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64-el.txt index d11e39f70ea..73492f3055b 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64-el.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64-el.txt @@ -15,5 +15,12 @@ 0x21 0x10 0x00 0x46 # CHECK: cvt.d.s $f0, $f2 0x21 0x10 0x80 0x46 # CHECK: cvt.d.w $f0, $f2 0x20 0x10 0x20 0x46 # CHECK: cvt.s.d $f0, $f2 +0x21 0x81 0xa0 0x46 # CHECK: cvt.d.l $f4, $f16 +0xe0 0xf3 0xa0 0x46 # CHECK: cvt.s.l $f15, $f30 +0xa0 0xd3 0xc0 0x46 # CHECK: cvt.s.pu $f14, $f26 +0xa6 0x90 0x14 0x46 # CHECK: cvt.ps.s $f2, $f18, $f20 +0xa8 0x17 0xc0 0x46 # CHECK: cvt.s.pl $f30, $f2 +0x2c 0x46 0xde 0x46 # CHECK: pll.ps $f24, $f8, $f30 +0x2d 0xd0 0xdc 0x46 # CHECK: plu.ps $f0, $f26, $f28 0x00 0x00 0xe4 0x44 # CHECK: mthc1 $4, $f0 0x00 0x00 0x64 0x44 # CHECK: mfhc1 $4, $f0 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64.txt b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64.txt index 28404df6acf..84eacd20f4a 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64.txt @@ -15,5 +15,12 @@ 0x46 0x00 0x10 0x21 # CHECK: cvt.d.s $f0, $f2 0x46 0x80 0x10 0x21 # CHECK: cvt.d.w $f0, $f2 0x46 0x20 0x10 0x20 # CHECK: cvt.s.d $f0, $f2 +0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16 +0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30 +0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26 +0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20 +0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2 +0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30 +0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28 0x44 0xe4 0x00 0x00 # CHECK: mthc1 $4, $f0 0x44 0x64 0x00 0x00 # CHECK: mfhc1 $4, $f0 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64-el.txt b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64-el.txt index f2e52f02caa..68906e83b98 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64-el.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64-el.txt @@ -15,5 +15,12 @@ 0x21 0x10 0x00 0x46 # CHECK: cvt.d.s $f0, $f2 0x21 0x10 0x80 0x46 # CHECK: cvt.d.w $f0, $f2 0x20 0x10 0x20 0x46 # CHECK: cvt.s.d $f0, $f2 +0x21 0x81 0xa0 0x46 # CHECK: cvt.d.l $f4, $f16 +0xe0 0xf3 0xa0 0x46 # CHECK: cvt.s.l $f15, $f30 +0xa0 0xd3 0xc0 0x46 # CHECK: cvt.s.pu $f14, $f26 +0xa6 0x90 0x14 0x46 # CHECK: cvt.ps.s $f2, $f18, $f20 +0xa8 0x17 0xc0 0x46 # CHECK: cvt.s.pl $f30, $f2 +0x2c 0x46 0xde 0x46 # CHECK: pll.ps $f24, $f8, $f30 +0x2d 0xd0 0xdc 0x46 # CHECK: plu.ps $f0, $f26, $f28 0x00 0x00 0xe4 0x44 # CHECK: mthc1 $4, $f0 0x00 0x00 0x64 0x44 # CHECK: mfhc1 $4, $f0 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64.txt b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64.txt index 1124b4dae87..48f31bc2827 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64.txt @@ -15,5 +15,12 @@ 0x46 0x00 0x10 0x21 # CHECK: cvt.d.s $f0, $f2 0x46 0x80 0x10 0x21 # CHECK: cvt.d.w $f0, $f2 0x46 0x20 0x10 0x20 # CHECK: cvt.s.d $f0, $f2 +0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16 +0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30 +0x46 0xc0 0xd3 0xa0 # CHECK: cvt.s.pu $f14, $f26 +0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20 +0x46 0xc0 0x17 0xa8 # CHECK: cvt.s.pl $f30, $f2 +0x46 0xde 0x46 0x2c # CHECK: pll.ps $f24, $f8, $f30 +0x46 0xdc 0xd0 0x2d # CHECK: plu.ps $f0, $f26, $f28 0x44 0xe4 0x00 0x00 # CHECK: mthc1 $4, $f0 0x44 0x64 0x00 0x00 # CHECK: mfhc1 $4, $f0 diff --git a/llvm/test/MC/Mips/mips1/invalid-mips5-wrong-error.s b/llvm/test/MC/Mips/mips1/invalid-mips5-wrong-error.s index 0564c1a250c..7cdbd89f1d4 100644 --- a/llvm/test/MC/Mips/mips1/invalid-mips5-wrong-error.s +++ b/llvm/test/MC/Mips/mips1/invalid-mips5-wrong-error.s @@ -25,9 +25,6 @@ c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction @@ -39,8 +36,6 @@ neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction diff --git a/llvm/test/MC/Mips/mips1/invalid-mips5.s b/llvm/test/MC/Mips/mips1/invalid-mips5.s index 1d7a864d2f5..d309385c3d8 100644 --- a/llvm/test/MC/Mips/mips1/invalid-mips5.s +++ b/llvm/test/MC/Mips/mips1/invalid-mips5.s @@ -15,6 +15,9 @@ cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled daddiu $k0,$s6,-4586 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -68,6 +71,8 @@ movz $a1,$s6,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.d $f12,$f29,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled round.w.d $f6,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/llvm/test/MC/Mips/mips2/invalid-mips5-wrong-error.s b/llvm/test/MC/Mips/mips2/invalid-mips5-wrong-error.s index 5eaeaa2a988..199f2ce3891 100644 --- a/llvm/test/MC/Mips/mips2/invalid-mips5-wrong-error.s +++ b/llvm/test/MC/Mips/mips2/invalid-mips5-wrong-error.s @@ -25,9 +25,6 @@ c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction @@ -39,8 +36,6 @@ neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction diff --git a/llvm/test/MC/Mips/mips2/invalid-mips5.s b/llvm/test/MC/Mips/mips2/invalid-mips5.s index ea563372fc1..7485f6dcb78 100644 --- a/llvm/test/MC/Mips/mips2/invalid-mips5.s +++ b/llvm/test/MC/Mips/mips2/invalid-mips5.s @@ -13,6 +13,9 @@ cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled daddiu $k0,$s6,-4586 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -64,6 +67,8 @@ movz $a1,$s6,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.d $f12,$f29,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/llvm/test/MC/Mips/mips3/invalid-mips5-wrong-error.s b/llvm/test/MC/Mips/mips3/invalid-mips5-wrong-error.s index 6cfd1625d12..43b9bfdf06d 100644 --- a/llvm/test/MC/Mips/mips3/invalid-mips5-wrong-error.s +++ b/llvm/test/MC/Mips/mips3/invalid-mips5-wrong-error.s @@ -25,9 +25,6 @@ c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction @@ -39,8 +36,6 @@ neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction diff --git a/llvm/test/MC/Mips/mips3/invalid-mips5.s b/llvm/test/MC/Mips/mips3/invalid-mips5.s index f851e1304ba..15928d59a7d 100644 --- a/llvm/test/MC/Mips/mips3/invalid-mips5.s +++ b/llvm/test/MC/Mips/mips3/invalid-mips5.s @@ -7,6 +7,9 @@ .set noat bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ldxc1 $f8,$s7($t3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -27,6 +30,8 @@ movz $a1,$s6,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.d $f12,$f29,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled sdxc1 $f11,$a6($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/llvm/test/MC/Mips/mips4/invalid-mips5-wrong-error.s b/llvm/test/MC/Mips/mips4/invalid-mips5-wrong-error.s index 5c8ab23539b..c7a07bf286b 100644 --- a/llvm/test/MC/Mips/mips4/invalid-mips5-wrong-error.s +++ b/llvm/test/MC/Mips/mips4/invalid-mips5-wrong-error.s @@ -25,9 +25,6 @@ c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction @@ -39,8 +36,6 @@ neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction diff --git a/llvm/test/MC/Mips/mips4/invalid-mips5.s b/llvm/test/MC/Mips/mips4/invalid-mips5.s index 8c0db00b88c..04526fc1e15 100644 --- a/llvm/test/MC/Mips/mips4/invalid-mips5.s +++ b/llvm/test/MC/Mips/mips4/invalid-mips5.s @@ -7,3 +7,8 @@ .set noat luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
\ No newline at end of file diff --git a/llvm/test/MC/Mips/mips64r2/valid-xfail.s b/llvm/test/MC/Mips/mips64r2/valid-xfail.s index 90cd760712c..f043b6b934e 100644 --- a/llvm/test/MC/Mips/mips64r2/valid-xfail.s +++ b/llvm/test/MC/Mips/mips64r2/valid-xfail.s @@ -28,9 +28,6 @@ c.ule.ps $fcc6,$f17,$f3 c.ult.ps $fcc7,$f14,$f0 c.un.ps $fcc4,$f2,$f26 - cvt.ps.s $f3,$f18,$f19 - cvt.s.pl $f30,$f1 - cvt.s.pu $f14,$f25 dmfc0 $10,c0_watchhi,2 dmfgc0 $gp,c0_perfcnt,6 dmt $k0 @@ -66,8 +63,6 @@ neg.ps $f19,$f13 nmadd.ps $f27,$f4,$f9,$f25 nmsub.ps $f6,$f12,$f14,$f17 - pll.ps $f25,$f9,$f30 - plu.ps $f1,$f26,$f29 preceq.w.phl $s8,$gp preceq.w.phr $s5,$15 pul.ps $f9,$f30,$f26 diff --git a/llvm/test/MC/Mips/mips64r2/valid.s b/llvm/test/MC/Mips/mips64r2/valid.s index dc62ddeb29a..c093102d759 100644 --- a/llvm/test/MC/Mips/mips64r2/valid.s +++ b/llvm/test/MC/Mips/mips64r2/valid.s @@ -103,6 +103,12 @@ a: # CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64 cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24] # CHECK: # <MCInst #{{[0-9]+}} CVT_W_S + cvt.ps.s $f4,$f18,$f20 # CHECK: cvt.ps.s $f4, $f18, $f20 # encoding: [0x46,0x14,0x91,0x26] + # CHECK: # <MCInst #{{[0-9]+}} CVT_PS_S64 + cvt.s.pl $f30,$f2 # CHECK: cvt.s.pl $f30, $f2 # encoding: [0x46,0xc0,0x17,0xa8] + # CHECK: # <MCInst #{{[0-9]+}} CVT_S_PL64 + cvt.s.pu $f14,$f26 # CHECK: cvt.s.pu $f14, $f26 # encoding: [0x46,0xc0,0xd3,0xa0] + # CHECK: # <MCInst #{{[0-9]+}} CVT_S_PU64 dadd $s3,$at,$ra dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] @@ -283,6 +289,10 @@ a: pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] # CHECK-NEXT: # <MCInst #{{[0-9]+}} PAUSE # CHECK-NOT # <MCInst #{{[0-9}+}} PAUSE_MM + pll.ps $f26,$f10,$f30 # CHECK: pll.ps $f26, $f10, $f30 # encoding: [0x46,0xde,0x56,0xac] + # CHECK: # <MCInst #{{[0-9]+}} PLL_PS64 + plu.ps $f2,$f26,$f30 # CHECK: plu.ps $f2, $f26, $f30 # encoding: [0x46,0xde,0xd0,0xad] + # CHECK: # <MCInst #{{[0-9]+}} PLU_PS64 pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] # FIXME: Use the code generator in order to print the .set directives # instead of the instruction printer. diff --git a/llvm/test/MC/Mips/mips64r3/valid-xfail.s b/llvm/test/MC/Mips/mips64r3/valid-xfail.s index 15c59f3f896..319db7d6a83 100644 --- a/llvm/test/MC/Mips/mips64r3/valid-xfail.s +++ b/llvm/test/MC/Mips/mips64r3/valid-xfail.s @@ -31,9 +31,6 @@ c.ule.ps $fcc6,$f17,$f3 c.ult.ps $fcc7,$f14,$f0 c.un.ps $fcc4,$f2,$f26 - cvt.ps.s $f3,$f18,$f19 - cvt.s.pl $f30,$f1 - cvt.s.pu $f14,$f25 dmfc0 $10,c0_watchhi,2 dmfgc0 $gp,c0_perfcnt,6 dmt $k0 @@ -69,8 +66,6 @@ neg.ps $f19,$f13 nmadd.ps $f27,$f4,$f9,$f25 nmsub.ps $f6,$f12,$f14,$f17 - pll.ps $f25,$f9,$f30 - plu.ps $f1,$f26,$f29 preceq.w.phl $s8,$gp preceq.w.phr $s5,$15 pul.ps $f9,$f30,$f26 diff --git a/llvm/test/MC/Mips/mips64r3/valid.s b/llvm/test/MC/Mips/mips64r3/valid.s index e3a2e5a88aa..84c2c443f78 100644 --- a/llvm/test/MC/Mips/mips64r3/valid.s +++ b/llvm/test/MC/Mips/mips64r3/valid.s @@ -103,6 +103,12 @@ a: # CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64 cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24] # CHECK: # <MCInst #{{[0-9]+}} CVT_W_S + cvt.ps.s $f4,$f18,$f20 # CHECK: cvt.ps.s $f4, $f18, $f20 # encoding: [0x46,0x14,0x91,0x26] + # CHECK: # <MCInst #{{[0-9]+}} CVT_PS_S64 + cvt.s.pl $f30,$f2 # CHECK: cvt.s.pl $f30, $f2 # encoding: [0x46,0xc0,0x17,0xa8] + # CHECK: # <MCInst #{{[0-9]+}} CVT_S_PL64 + cvt.s.pu $f14,$f26 # CHECK: cvt.s.pu $f14, $f26 # encoding: [0x46,0xc0,0xd3,0xa0] + # CHECK: # <MCInst #{{[0-9]+}} CVT_S_PU64 dadd $s3,$at,$ra dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] @@ -277,6 +283,10 @@ a: pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] # CHECK-NEXT: # <MCInst #{{[0-9]+}} PAUSE # CHECK-NOT # <MCInst #{{[0-9}+}} PAUSE_MM + pll.ps $f26,$f10,$f30 # CHECK: pll.ps $f26, $f10, $f30 # encoding: [0x46,0xde,0x56,0xac] + # CHECK: # <MCInst #{{[0-9]+}} PLL_PS64 + plu.ps $f2,$f26,$f30 # CHECK: plu.ps $f2, $f26, $f30 # encoding: [0x46,0xde,0xd0,0xad] + # CHECK: # <MCInst #{{[0-9]+}} PLU_PS64 pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] # FIXME: Use the code generator in order to print the .set directives # instead of the instruction printer. diff --git a/llvm/test/MC/Mips/mips64r5/valid-xfail.s b/llvm/test/MC/Mips/mips64r5/valid-xfail.s index 1ba984bdf90..23805c5f0f8 100644 --- a/llvm/test/MC/Mips/mips64r5/valid-xfail.s +++ b/llvm/test/MC/Mips/mips64r5/valid-xfail.s @@ -31,9 +31,6 @@ c.ule.ps $fcc6,$f17,$f3 c.ult.ps $fcc7,$f14,$f0 c.un.ps $fcc4,$f2,$f26 - cvt.ps.s $f3,$f18,$f19 - cvt.s.pl $f30,$f1 - cvt.s.pu $f14,$f25 dmfc0 $10,c0_watchhi,2 dmfgc0 $gp,c0_perfcnt,6 dmt $k0 @@ -69,8 +66,6 @@ neg.ps $f19,$f13 nmadd.ps $f27,$f4,$f9,$f25 nmsub.ps $f6,$f12,$f14,$f17 - pll.ps $f25,$f9,$f30 - plu.ps $f1,$f26,$f29 preceq.w.phl $s8,$gp preceq.w.phr $s5,$15 pul.ps $f9,$f30,$f26 diff --git a/llvm/test/MC/Mips/mips64r5/valid.s b/llvm/test/MC/Mips/mips64r5/valid.s index 1bf87ce54c9..13069d08992 100644 --- a/llvm/test/MC/Mips/mips64r5/valid.s +++ b/llvm/test/MC/Mips/mips64r5/valid.s @@ -103,6 +103,12 @@ a: # CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64 cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24] # CHECK: # <MCInst #{{[0-9]+}} CVT_W_S + cvt.ps.s $f4,$f18,$f20 # CHECK: cvt.ps.s $f4, $f18, $f20 # encoding: [0x46,0x14,0x91,0x26] + # CHECK: # <MCInst #{{[0-9]+}} CVT_PS_S64 + cvt.s.pl $f30,$f2 # CHECK: cvt.s.pl $f30, $f2 # encoding: [0x46,0xc0,0x17,0xa8] + # CHECK: # <MCInst #{{[0-9]+}} CVT_S_PL64 + cvt.s.pu $f14,$f26 # CHECK: cvt.s.pu $f14, $f26 # encoding: [0x46,0xc0,0xd3,0xa0] + # CHECK: # <MCInst #{{[0-9]+}} CVT_S_PU64 dadd $s3,$at,$ra dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] @@ -279,6 +285,10 @@ a: pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] # CHECK-NEXT: # <MCInst #{{[0-9]+}} PAUSE # CHECK-NOT # <MCInst #{{[0-9}+}} PAUSE_MM + pll.ps $f26,$f10,$f30 # CHECK: pll.ps $f26, $f10, $f30 # encoding: [0x46,0xde,0x56,0xac] + # CHECK: # <MCInst #{{[0-9]+}} PLL_PS64 + plu.ps $f2,$f26,$f30 # CHECK: plu.ps $f2, $f26, $f30 # encoding: [0x46,0xde,0xd0,0xad] + # CHECK: # <MCInst #{{[0-9]+}} PLU_PS64 pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] # FIXME: Use the code generator in order to print the .set directives # instead of the instruction printer. diff --git a/llvm/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s b/llvm/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s index ceeb5772235..0758164d0c7 100644 --- a/llvm/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s +++ b/llvm/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s @@ -28,7 +28,6 @@ c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction cvt.ps.pw $f3,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction @@ -41,8 +40,6 @@ neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction |
