diff options
| -rw-r--r-- | llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir index 64c65a41a31..d520750ba30 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir @@ -4,6 +4,8 @@ define void @test_add_s16() { ret void } define void @test_add_s8() { ret void } define void @test_add_s1() { ret void } + + define void @test_loads() { ret void } ... --- name: test_add_s32 @@ -109,3 +111,33 @@ body: | BX_RET 14, _, implicit %r0 ... +--- +name: test_loads +# CHECK-LABEL: name: test_loads +legalized: true +regBankSelected: false +selected: false +# CHECK: registers: +# CHECK: - { id: 0, class: gprb } +# CHECK: - { id: 1, class: gprb } +# CHECK: - { id: 2, class: gprb } +# CHECK: - { id: 3, class: gprb } +# CHECK: - { id: 4, class: gprb } + +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } +body: | + bb.0: + liveins: %r0 + %0(p0) = COPY %r0 + %1(s32) = G_LOAD %0 + %2(s16) = G_LOAD %0 + %3(s8) = G_LOAD %0 + %4(s1) = G_LOAD %0 + BX_RET 14, _, implicit %r0 + +... |
