diff options
| -rw-r--r-- | llvm/lib/Target/ARM/ARMTargetMachine.cpp | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/O3-pipeline.ll | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll | 13 |
4 files changed, 11 insertions, 17 deletions
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp index bd075cda2e4..d0138274d57 100644 --- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp +++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp @@ -403,11 +403,9 @@ void ARMPassConfig::addIRPasses() { TargetPassConfig::addIRPasses(); - // Run the parallel DSP pass and its helpers. - if (getOptLevel() == CodeGenOpt::Aggressive) { - addPass(createEarlyCSEPass()); + // Run the parallel DSP pass. + if (getOptLevel() == CodeGenOpt::Aggressive) addPass(createARMParallelDSPPass()); - } // Match interleaved memory accesses to ldN/stN intrinsics. if (TM->getOptLevel() != CodeGenOpt::None) diff --git a/llvm/test/CodeGen/ARM/O3-pipeline.ll b/llvm/test/CodeGen/ARM/O3-pipeline.ll index d9ec9c8e8ea..20bb06ed4be 100644 --- a/llvm/test/CodeGen/ARM/O3-pipeline.ll +++ b/llvm/test/CodeGen/ARM/O3-pipeline.ll @@ -33,7 +33,6 @@ ; CHECK: Scalarize Masked Memory Intrinsics ; CHECK: Expand reduction intrinsics ; CHECK: Dominator Tree Construction -; CHECK: Early CSE ; CHECK: Natural Loop Information ; CHECK: Scalar Evolution Analysis ; CHECK: Basic Alias Analysis (stateless AA impl) diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll b/llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll index 93ac0f5ef2e..03c77eb80dc 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll @@ -31,15 +31,11 @@ entry: %inc11.us.i.3.i = add i32 %idx, 4 br label %for.body +; TODO: CSE, or something similar, is required to remove the duplicate loads. ; CHECK: %for.body ; CHECK: smlad ; CHECK: smlad -; CHECK: smlad -; CHECK: smlad -; CHECK: smlad -; CHECK: smlad -; CHECK: smlad -; CHECK: smlad +; CHECK-NOT: smlad r{{.*}} for.body: %A3 = phi i32 [ %add9.us.i.3361.i, %for.body ], [ 0, %entry ] diff --git a/llvm/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll b/llvm/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll index e043773f5cc..34569e9116f 100644 --- a/llvm/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll +++ b/llvm/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll @@ -32,12 +32,13 @@ define fastcc i32 @parse_percent_token() nounwind { entry: -; CHECK: bx lr -; CHECK: bx lr -; CHECK: bx lr -; CHECK: bx lr -; CHECK: bx lr -; CHECK: bx lr +; CHECK: pop +; CHECK: pop +; CHECK: pop +; CHECK: pop +; CHECK: pop +; CHECK: pop +; CHECK: pop ; Do not convert into single stream code. BranchProbability Analysis assumes ; that branches which goes to "ret" instruction have lower probabilities. switch i32 undef, label %bb7 [ |
