diff options
| -rw-r--r-- | llvm/lib/Target/Mips/MipsLegalizerInfo.cpp | 15 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/GlobalISel/legalizer/trap.mir | 22 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/trap.ll | 14 |
3 files changed, 50 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp index d4de79c10a2..80a24a3ab42 100644 --- a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp +++ b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp @@ -219,8 +219,16 @@ bool MipsLegalizerInfo::legalizeCustom(MachineInstr &MI, return true; } -bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, +bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI, + MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder) const { + const MipsSubtarget &ST = + static_cast<const MipsSubtarget &>(MI.getMF()->getSubtarget()); + const MipsInstrInfo &TII = *ST.getInstrInfo(); + const MipsRegisterInfo &TRI = *ST.getRegisterInfo(); + const RegisterBankInfo &RBI = *ST.getRegBankInfo(); + MIRBuilder.setInstr(MI); + switch (MI.getIntrinsicID()) { case Intrinsic::memcpy: case Intrinsic::memset: @@ -230,6 +238,11 @@ bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo return false; MI.eraseFromParent(); return true; + case Intrinsic::trap: { + MachineInstr *Trap = MIRBuilder.buildInstr(Mips::TRAP); + MI.eraseFromParent(); + return constrainSelectedInstRegOperands(*Trap, TII, TRI, RBI); + } default: break; } diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/trap.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/trap.mir new file mode 100644 index 00000000000..101a12490b7 --- /dev/null +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/trap.mir @@ -0,0 +1,22 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 +--- | + + declare void @llvm.trap() + define void @f() { ret void } + +... +--- +name: f +alignment: 2 +body: | + bb.1 (%ir-block.0): + ; MIPS32-LABEL: name: f + ; MIPS32: TRAP + ; MIPS32: RetRA + G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap) + RetRA + +... + + diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/trap.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/trap.ll new file mode 100644 index 00000000000..cf71f5f5677 --- /dev/null +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/trap.ll @@ -0,0 +1,14 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32 + + declare void @llvm.trap() + + define void @f() { +; MIPS32-LABEL: f: +; MIPS32: # %bb.0: +; MIPS32-NEXT: break +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop + call void @llvm.trap() + ret void + } |
