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-rw-r--r--polly/lib/Analysis/ScopInfo.cpp24
-rw-r--r--polly/test/ScopInfo/NonAffine/non_affine_loop_used_later.ll2
-rw-r--r--polly/test/ScopInfo/intra-non-affine-stmt-phi-node.ll4
-rw-r--r--polly/test/ScopInfo/non_affine_region_2.ll2
-rw-r--r--polly/test/ScopInfo/non_affine_region_3.ll6
-rw-r--r--polly/test/ScopInfo/non_affine_region_4.ll2
6 files changed, 24 insertions, 16 deletions
diff --git a/polly/lib/Analysis/ScopInfo.cpp b/polly/lib/Analysis/ScopInfo.cpp
index d37dd681c71..78b3d847e87 100644
--- a/polly/lib/Analysis/ScopInfo.cpp
+++ b/polly/lib/Analysis/ScopInfo.cpp
@@ -3885,14 +3885,22 @@ void ScopInfo::addMemoryAccess(BasicBlock *BB, Instruction *Inst,
Value *BaseAddr = BaseAddress;
std::string BaseName = getIslCompatibleName("MemRef_", BaseAddr, "");
- // The execution of a store is not guaranteed if its parent block is not
- // guaranteed to executed, here tested by checking whether it dominates the
- // exit block. However, implicit writes (llvm::Value definitions or one of a
- // PHI's incoming values) must occur in well-formed IR code.
- bool isApproximated = (Kind == ScopArrayInfo::MK_Array) &&
- Stmt->isRegionStmt() &&
- !DT->dominates(BB, Stmt->getRegion()->getExit());
- if (isApproximated && Type == MemoryAccess::MUST_WRITE)
+ bool isKnownMustAccess = false;
+
+ // Accesses in single-basic block statements are always excuted.
+ if (Stmt->isBlockStmt())
+ isKnownMustAccess = true;
+
+ if (Stmt->isRegionStmt()) {
+ // Accesses that dominate the exit block of a non-affine region are always
+ // executed. In non-affine regions there may exist MK_Values that do not
+ // dominate the exit. MK_Values will always dominate the exit and MK_PHIs
+ // only if there is at most one PHI_WRITE in the non-affine region.
+ if (DT->dominates(BB, Stmt->getRegion()->getExit()))
+ isKnownMustAccess = true;
+ }
+
+ if (!isKnownMustAccess && Type == MemoryAccess::MUST_WRITE)
Type = MemoryAccess::MAY_WRITE;
AccList.emplace_back(Stmt, Inst, Type, BaseAddress, ElemBytes, Affine,
diff --git a/polly/test/ScopInfo/NonAffine/non_affine_loop_used_later.ll b/polly/test/ScopInfo/NonAffine/non_affine_loop_used_later.ll
index 53ee464b318..231d014a473 100644
--- a/polly/test/ScopInfo/NonAffine/non_affine_loop_used_later.ll
+++ b/polly/test/ScopInfo/NonAffine/non_affine_loop_used_later.ll
@@ -39,7 +39,7 @@
; CHECK: [N] -> { Stmt_bb4__TO__bb18[i0] -> MemRef_A[i0] };
; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N] -> { Stmt_bb4__TO__bb18[i0] -> MemRef_smax[] };
-; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
+; CHECK: MayWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N] -> { Stmt_bb4__TO__bb18[i0] -> MemRef_j_2__phi[] };
; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: [N] -> { Stmt_bb4__TO__bb18[i0] -> MemRef_j_0[] };
diff --git a/polly/test/ScopInfo/intra-non-affine-stmt-phi-node.ll b/polly/test/ScopInfo/intra-non-affine-stmt-phi-node.ll
index 3b431b4413f..8a27811748a 100644
--- a/polly/test/ScopInfo/intra-non-affine-stmt-phi-node.ll
+++ b/polly/test/ScopInfo/intra-non-affine-stmt-phi-node.ll
@@ -10,9 +10,9 @@
; CHECK-NEXT: { Stmt_loop__TO__backedge[i0] -> [i0, 0] };
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_loop__TO__backedge[i0] -> MemRef_merge__phi[] };
-; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
+; CHECK-NEXT: MayWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_loop__TO__backedge[i0] -> MemRef_merge__phi[] };
-; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
+; CHECK-NEXT: MayWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_loop__TO__backedge[i0] -> MemRef_merge__phi[] };
; CHECK-NEXT: Stmt_backedge
; CHECK-NEXT: Domain :=
diff --git a/polly/test/ScopInfo/non_affine_region_2.ll b/polly/test/ScopInfo/non_affine_region_2.ll
index 8d1779b99dc..f549694e9ac 100644
--- a/polly/test/ScopInfo/non_affine_region_2.ll
+++ b/polly/test/ScopInfo/non_affine_region_2.ll
@@ -35,7 +35,7 @@
; CHECK-NEXT: { Stmt_bb3__TO__bb18[i0] -> MemRef_A[i0] };
; CHECK-NOT: { Stmt_bb3__TO__bb18[i0] -> MemRef_x_0[] };
; CHECK-NOT: { Stmt_bb3__TO__bb18[i0] -> MemRef_x_1[] };
-; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
+; CHECK: MayWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_bb3__TO__bb18[i0] -> MemRef_x_2__phi[] };
; CHECK-NOT: { Stmt_bb3__TO__bb18[i0] -> MemRef_x_0[] };
; CHECK-NOT: { Stmt_bb3__TO__bb18[i0] -> MemRef_x_1[] };
diff --git a/polly/test/ScopInfo/non_affine_region_3.ll b/polly/test/ScopInfo/non_affine_region_3.ll
index 488115cdc92..cb7197bbe28 100644
--- a/polly/test/ScopInfo/non_affine_region_3.ll
+++ b/polly/test/ScopInfo/non_affine_region_3.ll
@@ -31,11 +31,11 @@
; CHECK: { Stmt_bb3__TO__bb18[i0] -> [i0, 0] };
; CHECK: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
; CHECK: { Stmt_bb3__TO__bb18[i0] -> MemRef_A[i0] };
-; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
+; CHECK: MayWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: { Stmt_bb3__TO__bb18[i0] -> MemRef_x_2__phi[] };
-; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
+; CHECK: MayWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: { Stmt_bb3__TO__bb18[i0] -> MemRef_x_2__phi[] };
-; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
+; CHECK: MayWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: { Stmt_bb3__TO__bb18[i0] -> MemRef_x_2__phi[] };
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: { Stmt_bb3__TO__bb18[i0] -> MemRef_x_2__phi[] };
diff --git a/polly/test/ScopInfo/non_affine_region_4.ll b/polly/test/ScopInfo/non_affine_region_4.ll
index 7a65e042c4b..a2a78b6a45e 100644
--- a/polly/test/ScopInfo/non_affine_region_4.ll
+++ b/polly/test/ScopInfo/non_affine_region_4.ll
@@ -39,7 +39,7 @@
; CHECK: { Stmt_bb2__TO__bb7[i0] -> MemRef_A[i0] };
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: { Stmt_bb2__TO__bb7[i0] -> MemRef_x[] };
-; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
+; CHECK: MayWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: { Stmt_bb2__TO__bb7[i0] -> MemRef_y__phi[] };
; CHECK: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK: { Stmt_bb2__TO__bb7[i0] -> MemRef_y__phi[] };
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