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-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrInfo.cpp2
-rw-r--r--llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll2
-rw-r--r--llvm/test/CodeGen/PowerPC/f128-conv.ll14
-rw-r--r--llvm/test/CodeGen/PowerPC/f128-passByValue.ll4
-rw-r--r--llvm/test/CodeGen/PowerPC/p9_copy_fp.ll48
-rw-r--r--llvm/test/CodeGen/PowerPC/vsx-spill.ll8
6 files changed, 63 insertions, 15 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index ca84f4ba5b1..3e401981ccb 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -987,7 +987,7 @@ void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
Opc = PPC::XXLOR;
else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
PPC::VSSRCRegClass.contains(DestReg, SrcReg))
- Opc = PPC::XXLORf;
+ Opc = (Subtarget.hasP9Vector()) ? PPC::XSCPSGNDP : PPC::XXLORf;
else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
Opc = PPC::QVFMR;
else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll
index d4e5f8554e0..498318f5546 100644
--- a/llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll
@@ -96,7 +96,7 @@ entry:
ret double %0
; CHECK-LABEL: testTruncOdd
; CHECK: xscvqpdpo v2, v2
-; CHECK: xxlor f1, v2, v2
+; CHECK: xscpsgndp f1, v2, v2
; CHECK: blr
}
diff --git a/llvm/test/CodeGen/PowerPC/f128-conv.ll b/llvm/test/CodeGen/PowerPC/f128-conv.ll
index 4ac0a009974..6c8d5964cb3 100644
--- a/llvm/test/CodeGen/PowerPC/f128-conv.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-conv.ll
@@ -414,7 +414,7 @@ define double @qpConv2dp(fp128* nocapture readonly %a) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xscvqpdp v2, v2
-; CHECK-NEXT: xxlor f1, v2, v2
+; CHECK-NEXT: xscpsgndp f1, v2, v2
; CHECK-NEXT: blr
entry:
%0 = load fp128, fp128* %a, align 16
@@ -559,7 +559,7 @@ entry:
define fp128 @dpConv2qp(double %a) {
; CHECK-LABEL: dpConv2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxlor v2, f1, f1
+; CHECK-NEXT: xscpsgndp v2, f1, f1
; CHECK-NEXT: xscvdpqp v2, v2
; CHECK-NEXT: blr
entry:
@@ -608,7 +608,7 @@ entry:
define void @dpConv2qp_03(fp128* nocapture %res, i32 signext %idx, double %a) {
; CHECK-LABEL: dpConv2qp_03:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxlor v2, f1, f1
+; CHECK-NEXT: xscpsgndp v2, f1, f1
; CHECK-NEXT: sldi r4, r4, 4
; CHECK-NEXT: xscvdpqp v2, v2
; CHECK-NEXT: stxvx v2, r3, r4
@@ -625,7 +625,7 @@ entry:
define void @dpConv2qp_04(double %a, fp128* nocapture %res) {
; CHECK-LABEL: dpConv2qp_04:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxlor v2, f1, f1
+; CHECK-NEXT: xscpsgndp v2, f1, f1
; CHECK-NEXT: xscvdpqp v2, v2
; CHECK-NEXT: stxv v2, 0(r4)
; CHECK-NEXT: blr
@@ -639,7 +639,7 @@ entry:
define fp128 @spConv2qp(float %a) {
; CHECK-LABEL: spConv2qp:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxlor v2, f1, f1
+; CHECK-NEXT: xscpsgndp v2, f1, f1
; CHECK-NEXT: xscvdpqp v2, v2
; CHECK-NEXT: blr
entry:
@@ -688,7 +688,7 @@ entry:
define void @spConv2qp_03(fp128* nocapture %res, i32 signext %idx, float %a) {
; CHECK-LABEL: spConv2qp_03:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxlor v2, f1, f1
+; CHECK-NEXT: xscpsgndp v2, f1, f1
; CHECK-NEXT: sldi r4, r4, 4
; CHECK-NEXT: xscvdpqp v2, v2
; CHECK-NEXT: stxvx v2, r3, r4
@@ -705,7 +705,7 @@ entry:
define void @spConv2qp_04(float %a, fp128* nocapture %res) {
; CHECK-LABEL: spConv2qp_04:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxlor v2, f1, f1
+; CHECK-NEXT: xscpsgndp v2, f1, f1
; CHECK-NEXT: xscvdpqp v2, v2
; CHECK-NEXT: stxv v2, 0(r4)
; CHECK-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/f128-passByValue.ll b/llvm/test/CodeGen/PowerPC/f128-passByValue.ll
index ad1de5112cc..467e5553ad1 100644
--- a/llvm/test/CodeGen/PowerPC/f128-passByValue.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-passByValue.ll
@@ -154,7 +154,7 @@ define fp128 @mixParam_02(fp128 %p1, double %p2, i64* nocapture %p3,
; CHECK: # %bb.0: # %entry
; CHECK-DAG: lwz r3, 96(r1)
; CHECK: add r4, r7, r9
-; CHECK-NEXT: xxlor v[[REG0:[0-9]+]], f1, f1
+; CHECK-NEXT: xscpsgndp v[[REG0:[0-9]+]], f1, f1
; CHECK-DAG: add r4, r4, r10
; CHECK: xscvdpqp v[[REG0]], v[[REG0]]
; CHECK-NEXT: add r3, r4, r3
@@ -186,7 +186,7 @@ define fastcc fp128 @mixParam_02f(fp128 %p1, double %p2, i64* nocapture %p3,
; CHECK-LABEL: mixParam_02f:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: add r4, r4, r6
-; CHECK-NEXT: xxlor v[[REG0:[0-9]+]], f1, f1
+; CHECK-NEXT: xscpsgndp v[[REG0:[0-9]+]], f1, f1
; CHECK-NEXT: add r4, r4, r7
; CHECK-NEXT: xscvdpqp v[[REG0]], v[[REG0]]
; CHECK-NEXT: add r4, r4, r8
diff --git a/llvm/test/CodeGen/PowerPC/p9_copy_fp.ll b/llvm/test/CodeGen/PowerPC/p9_copy_fp.ll
new file mode 100644
index 00000000000..ccc2b270f95
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/p9_copy_fp.ll
@@ -0,0 +1,48 @@
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=+vsx -ppc-vsr-nums-as-vr \
+; RUN: -mtriple=powerpc64le-unknown-linux-gnu -ppc-asm-full-reg-names < %s \
+; RUN: | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=+vsx -ppc-vsr-nums-as-vr \
+; RUN: -mtriple=powerpc64-unknown-linux-gnu -ppc-asm-full-reg-names < %s \
+; RUN: | FileCheck -check-prefix=CHECK-BE %s
+
+; Function Attrs: norecurse nounwind readnone
+define double @cp_fp1(<2 x double> %v) {
+ ; CHECK-LABEL: cp_fp1:
+ ; CHECK: xscpsgndp f1, v2, v2
+ ; CHECK: blr
+
+ ; CHECK-BE-LABEL: cp_fp1:
+ ; CHECK-BE: xxswapd vs1, v2
+ ; CHECK-BE: blr
+ entry:
+ %vecext = extractelement <2 x double> %v, i32 1
+ ret double %vecext
+}
+
+; Function Attrs: norecurse nounwind readnone
+define double @cp_fp2(<2 x double> %v) {
+ ; CHECK-LABEL: cp_fp2:
+ ; CHECK: xxswapd vs1, v2
+ ; CHECK: blr
+
+ ; CHECK-BE-LABEL: cp_fp2:
+ ; CHECK-BE: xscpsgndp f1, v2, v2
+ ; CHECK-BE: blr
+ entry:
+ %vecext = extractelement <2 x double> %v, i32 0
+ ret double %vecext
+}
+
+; Function Attrs: norecurse nounwind readnone
+define <2 x double> @cp_fp3(double %v) {
+ ; CHECK-LABEL: cp_fp3:
+ ; CHECK: xxspltd v2, vs1, 0
+ ; CHECK: blr
+
+ ; CHECK-BE-LABEL: cp_fp3:
+ ; CHECK-BE: xscpsgndp v2, f1, f1
+ ; CHECK-BE: blr
+ entry:
+ %vecins = insertelement <2 x double> undef, double %v, i32 0
+ ret <2 x double> %vecins
+}
diff --git a/llvm/test/CodeGen/PowerPC/vsx-spill.ll b/llvm/test/CodeGen/PowerPC/vsx-spill.ll
index 65e54dda08d..3bea07f3b8d 100644
--- a/llvm/test/CodeGen/PowerPC/vsx-spill.ll
+++ b/llvm/test/CodeGen/PowerPC/vsx-spill.ll
@@ -36,8 +36,8 @@ entry:
; CHECK-FISL: blr
; CHECK-P9-REG: @foo1
-; CHECK-P9-REG: xxlor v2, f1, f1
-; CHECK-P9-REG: xxlor f1, v2, v2
+; CHECK-P9-REG: xscpsgndp v2, f1, f1
+; CHECK-P9-REG: xscpsgndp f1, v2, v2
; CHECK-P9-REG: blr
; CHECK-P9-FISL: @foo1
@@ -66,8 +66,8 @@ entry:
; CHECK-FISL: blr
; CHECK-P9-REG: @foo2
-; CHECK-P9-REG: {{xxlor|xsadddp}} v2, f1, f1
-; CHECK-P9-REG: {{xxlor|xsadddp}} f1, v2, v2
+; CHECK-P9-REG: {{xscpsgndp|xsadddp}} v2, f1, f1
+; CHECK-P9-REG: {{xscpsgndp|xsadddp}} f1, v2, v2
; CHECK-P9-REG: blr
; CHECK-P9-FISL: @foo2
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