diff options
69 files changed, 69 insertions, 69 deletions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir index 679c6b4788f..63f852030e7 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir index cdd885cb673..75e1d516353 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir index 926a62761ce..29f83b36289 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir index d7d8ebeaf56..7b79991aae2 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir index abbac413f5c..16d9e59698f 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-div.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-div.mir index aaef45d3c92..c6e0aabfd2c 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-div.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-div.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir index 9907f009d93..70b55e4ebc6 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir index 72bd613fab3..8cdc7b78b1e 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir index 8d0af0dc447..f79d0382ea7 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-gep.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-gep.mir index 3f11c123ba5..d6ec983c206 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-gep.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-gep.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir index 9e1b5084d1e..0596314c60e 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir index 70ffc3ea3ac..69e72bcb1f3 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir index 00145ad1f53..29551135358 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir index 36726b7a30c..1ea6e9c292f 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir index 802d8ad1989..e8b85098246 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir index a693d18b8ca..a25d3951e1a 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir index bd8cdf4f1ae..50a4d93cbe2 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir index 5d95c5ee2d8..f75a2982a3f 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir index f06e998453d..cd24bccfe77 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir index 6652d2b4d7a..82a1dd09c1a 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir index 21def851959..8bda08d0a1d 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir index a2f3c8ea3b1..460b3d16f1c 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/CodeGen/AArch64/arm64-regress-opt-cmp.mir b/llvm/test/CodeGen/AArch64/arm64-regress-opt-cmp.mir index bda025af519..9ad47c721c3 100644 --- a/llvm/test/CodeGen/AArch64/arm64-regress-opt-cmp.mir +++ b/llvm/test/CodeGen/AArch64/arm64-regress-opt-cmp.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=aarch64-linux-gnu -run-pass peephole-opt -o - %s 2>&1 | FileCheck %s +# RUN: llc -mtriple=aarch64-linux-gnu -run-pass peephole-opt -o - %s | FileCheck %s # CHECK: %1 = ANDWri {{.*}} # CHECK-NEXT: %wzr = SUBSWri {{.*}} --- | diff --git a/llvm/test/CodeGen/AArch64/ldst-opt.mir b/llvm/test/CodeGen/AArch64/ldst-opt.mir index 85b655b717c..f7641d3ffd0 100644 --- a/llvm/test/CodeGen/AArch64/ldst-opt.mir +++ b/llvm/test/CodeGen/AArch64/ldst-opt.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=aarch64--linux-gnu -run-pass=aarch64-ldst-opt %s -verify-machineinstrs -o - 2>&1 | FileCheck %s +# RUN: llc -mtriple=aarch64--linux-gnu -run-pass=aarch64-ldst-opt %s -verify-machineinstrs -o - | FileCheck %s --- name: promote-load-from-store tracksRegLiveness: true diff --git a/llvm/test/CodeGen/AArch64/movimm-wzr.mir b/llvm/test/CodeGen/AArch64/movimm-wzr.mir index 093f85bd931..60e9bfa03a9 100644 --- a/llvm/test/CodeGen/AArch64/movimm-wzr.mir +++ b/llvm/test/CodeGen/AArch64/movimm-wzr.mir @@ -1,4 +1,4 @@ -# RUN: llc -run-pass=aarch64-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -run-pass=aarch64-expand-pseudo %s -o - | FileCheck %s --- | ; ModuleID = 'simple.ll' diff --git a/llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir index 475d5b39299..b1fc792d659 100644 --- a/llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit add with carry pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/ADDWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/ADDWRdRr.mir index 2205febcc93..5743b153633 100644 --- a/llvm/test/CodeGen/AVR/pseudo/ADDWRdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/ADDWRdRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit add pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir b/llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir index 5af8db15951..bcea4e6dfe2 100644 --- a/llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir +++ b/llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit ANDO pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir index c9458e9ba5d..f6b060a5d73 100644 --- a/llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit AND pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/ASRWRd.mir b/llvm/test/CodeGen/AVR/pseudo/ASRWRd.mir index 3e809564ca1..5253dcd87f1 100644 --- a/llvm/test/CodeGen/AVR/pseudo/ASRWRd.mir +++ b/llvm/test/CodeGen/AVR/pseudo/ASRWRd.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s --- | target triple = "avr--" diff --git a/llvm/test/CodeGen/AVR/pseudo/COMWRd.mir b/llvm/test/CodeGen/AVR/pseudo/COMWRd.mir index 282d601686a..58ff7af7cb3 100644 --- a/llvm/test/CodeGen/AVR/pseudo/COMWRd.mir +++ b/llvm/test/CodeGen/AVR/pseudo/COMWRd.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit COM pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir index 2081aa0b5ee..c0ab60e8929 100644 --- a/llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit CPCW pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir index 7e25e7fe227..c93c99151a4 100644 --- a/llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit CPW pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir index 8769c12cbb1..de53c2d077e 100644 --- a/llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit EOR pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/FRMIDX.mir b/llvm/test/CodeGen/AVR/pseudo/FRMIDX.mir index 47a9397fa6b..b56122a43ad 100644 --- a/llvm/test/CodeGen/AVR/pseudo/FRMIDX.mir +++ b/llvm/test/CodeGen/AVR/pseudo/FRMIDX.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # TODO: Write this test. # This instruction isn't expanded by the pseudo expansion passs, but diff --git a/llvm/test/CodeGen/AVR/pseudo/INWRdA.mir b/llvm/test/CodeGen/AVR/pseudo/INWRdA.mir index a801598fadd..1b2d7fa0f53 100644 --- a/llvm/test/CodeGen/AVR/pseudo/INWRdA.mir +++ b/llvm/test/CodeGen/AVR/pseudo/INWRdA.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s --- | target triple = "avr--" diff --git a/llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir b/llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir index 09d0b96164d..5ff2ef1742e 100644 --- a/llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir +++ b/llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 %s -o - 2>&1 -march=avr | FileCheck %s +# RUN: llc -O0 %s -o - -march=avr | FileCheck %s # This test checks the expansion of the 16-bit 'LDDWRdPtrQ' pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir b/llvm/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir index 7d3251adbda..831c75b38b1 100644 --- a/llvm/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir +++ b/llvm/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 %s -o - 2>&1 -march=avr | FileCheck %s +# RUN: llc -O0 %s -o - -march=avr | FileCheck %s # This test checks the expansion of the 16-bit 'LDDWRdYQ instruction diff --git a/llvm/test/CodeGen/AVR/pseudo/LDIWRdK.mir b/llvm/test/CodeGen/AVR/pseudo/LDIWRdK.mir index 23d16d9c569..f4788adf20b 100644 --- a/llvm/test/CodeGen/AVR/pseudo/LDIWRdK.mir +++ b/llvm/test/CodeGen/AVR/pseudo/LDIWRdK.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit LDIWRdK pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/LDSWRdK.mir b/llvm/test/CodeGen/AVR/pseudo/LDSWRdK.mir index aa4883634d7..b813923abcb 100644 --- a/llvm/test/CodeGen/AVR/pseudo/LDSWRdK.mir +++ b/llvm/test/CodeGen/AVR/pseudo/LDSWRdK.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit LDSWRdK pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr.mir b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr.mir index aaf9f182f2b..6db615878b9 100644 --- a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit LDWRdPtr pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir index f304cc220cb..eb65c6538d1 100644 --- a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir +++ b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit LDWRdPtrPd pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir index 9153be0bf1c..50bad2a4c76 100644 --- a/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir +++ b/llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit LDWRdPtrPi pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir b/llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir index 441939856ae..537944866e5 100644 --- a/llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir +++ b/llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s --- | target triple = "avr--" diff --git a/llvm/test/CodeGen/AVR/pseudo/LSRWRd.mir b/llvm/test/CodeGen/AVR/pseudo/LSRWRd.mir index f5ffb93f403..a1a513f4e36 100644 --- a/llvm/test/CodeGen/AVR/pseudo/LSRWRd.mir +++ b/llvm/test/CodeGen/AVR/pseudo/LSRWRd.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s --- | target triple = "avr--" diff --git a/llvm/test/CodeGen/AVR/pseudo/ORIWRdK.mir b/llvm/test/CodeGen/AVR/pseudo/ORIWRdK.mir index 92bc36769eb..d77a6ba8848 100644 --- a/llvm/test/CodeGen/AVR/pseudo/ORIWRdK.mir +++ b/llvm/test/CodeGen/AVR/pseudo/ORIWRdK.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit OR pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/ORWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/ORWRdRr.mir index f7a377ec860..834c21cba8f 100644 --- a/llvm/test/CodeGen/AVR/pseudo/ORWRdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/ORWRdRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit OR pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/OUTWARr.mir b/llvm/test/CodeGen/AVR/pseudo/OUTWARr.mir index 85e9f5259a8..99abad1c31b 100644 --- a/llvm/test/CodeGen/AVR/pseudo/OUTWARr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/OUTWARr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s --- | target triple = "avr--" diff --git a/llvm/test/CodeGen/AVR/pseudo/POPWRd.mir b/llvm/test/CodeGen/AVR/pseudo/POPWRd.mir index 6794742bf54..8bd7fe68727 100644 --- a/llvm/test/CodeGen/AVR/pseudo/POPWRd.mir +++ b/llvm/test/CodeGen/AVR/pseudo/POPWRd.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s --- | target triple = "avr--" diff --git a/llvm/test/CodeGen/AVR/pseudo/PUSHWRr.mir b/llvm/test/CodeGen/AVR/pseudo/PUSHWRr.mir index 93920867030..ec94ecbf5bb 100644 --- a/llvm/test/CodeGen/AVR/pseudo/PUSHWRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/PUSHWRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s --- | target triple = "avr--" diff --git a/llvm/test/CodeGen/AVR/pseudo/SBCIWRdK.mir b/llvm/test/CodeGen/AVR/pseudo/SBCIWRdK.mir index 9152c6d9126..644e6106ee7 100644 --- a/llvm/test/CodeGen/AVR/pseudo/SBCIWRdK.mir +++ b/llvm/test/CodeGen/AVR/pseudo/SBCIWRdK.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit subtraction with carry pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/SBCWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/SBCWRdRr.mir index 9159906b76a..5cf5d33252c 100644 --- a/llvm/test/CodeGen/AVR/pseudo/SBCWRdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/SBCWRdRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit subtraction with carry pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/SEXT.mir b/llvm/test/CodeGen/AVR/pseudo/SEXT.mir index 069eb883dcc..0d10358c10e 100644 --- a/llvm/test/CodeGen/AVR/pseudo/SEXT.mir +++ b/llvm/test/CodeGen/AVR/pseudo/SEXT.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s --- | target triple = "avr--" diff --git a/llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir b/llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir index ff2fdb9155e..9252997d489 100644 --- a/llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s --- | target triple = "avr--" diff --git a/llvm/test/CodeGen/AVR/pseudo/STSWKRr.mir b/llvm/test/CodeGen/AVR/pseudo/STSWKRr.mir index ccf852271ae..18f10180809 100644 --- a/llvm/test/CodeGen/AVR/pseudo/STSWKRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/STSWKRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit STSWRdK pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir b/llvm/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir index 0d0d9e909e4..d884d2121c2 100644 --- a/llvm/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s --- | target triple = "avr--" diff --git a/llvm/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir b/llvm/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir index a436d9b109b..962776aa633 100644 --- a/llvm/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s --- | target triple = "avr--" diff --git a/llvm/test/CodeGen/AVR/pseudo/STWPtrRr.mir b/llvm/test/CodeGen/AVR/pseudo/STWPtrRr.mir index f85f4f8a045..efed707bfe8 100644 --- a/llvm/test/CodeGen/AVR/pseudo/STWPtrRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/STWPtrRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit STSWRdK pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/SUBIWRdK.mir b/llvm/test/CodeGen/AVR/pseudo/SUBIWRdK.mir index 95c68c0a122..c7d88d7ab3f 100644 --- a/llvm/test/CodeGen/AVR/pseudo/SUBIWRdK.mir +++ b/llvm/test/CodeGen/AVR/pseudo/SUBIWRdK.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit subtraction pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/SUBWRdRr.mir b/llvm/test/CodeGen/AVR/pseudo/SUBWRdRr.mir index 9892cf5b7f3..b12b0e5349e 100644 --- a/llvm/test/CodeGen/AVR/pseudo/SUBWRdRr.mir +++ b/llvm/test/CodeGen/AVR/pseudo/SUBWRdRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s # This test checks the expansion of the 16-bit subtraction pseudo instruction. diff --git a/llvm/test/CodeGen/AVR/pseudo/ZEXT.mir b/llvm/test/CodeGen/AVR/pseudo/ZEXT.mir index 069eb883dcc..0d10358c10e 100644 --- a/llvm/test/CodeGen/AVR/pseudo/ZEXT.mir +++ b/llvm/test/CodeGen/AVR/pseudo/ZEXT.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s --- | target triple = "avr--" diff --git a/llvm/test/CodeGen/AVR/pseudo/expand-lddw-dst-src-same.mir b/llvm/test/CodeGen/AVR/pseudo/expand-lddw-dst-src-same.mir index 52945e6cf84..8427a2bfb4e 100644 --- a/llvm/test/CodeGen/AVR/pseudo/expand-lddw-dst-src-same.mir +++ b/llvm/test/CodeGen/AVR/pseudo/expand-lddw-dst-src-same.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 %s -o - 2>&1 -march=avr | FileCheck %s +# RUN: llc -O0 %s -o - -march=avr | FileCheck %s # This test ensures that the pseudo expander can correctly handle the case # where we are expanding a 16-bit LDD instruction where the source and diff --git a/llvm/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir b/llvm/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir index b43c7750832..7421bd4c4e8 100644 --- a/llvm/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir +++ b/llvm/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -run-pass=avr-relax-mem %s -o - 2>&1 | FileCheck %s +# RUN: llc -O0 -run-pass=avr-relax-mem %s -o - | FileCheck %s --- | target triple = "avr--" diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir b/llvm/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir index 983035e228c..4a4a5e143ee 100644 --- a/llvm/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir +++ b/llvm/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass expand-condsets -o - 2>&1 %s -verify-machineinstrs -debug-only=expand-condsets | FileCheck %s +# RUN: llc -march=hexagon -run-pass expand-condsets -o - %s -verify-machineinstrs -debug-only=expand-condsets | FileCheck %s # REQUIRES: asserts # Check that coalesced registers are removed from live intervals. diff --git a/llvm/test/CodeGen/MIR/Generic/llvmIRMissing.mir b/llvm/test/CodeGen/MIR/Generic/llvmIRMissing.mir index 9f361e8d3fe..9bd2a3e35a3 100644 --- a/llvm/test/CodeGen/MIR/Generic/llvmIRMissing.mir +++ b/llvm/test/CodeGen/MIR/Generic/llvmIRMissing.mir @@ -1,4 +1,4 @@ -# RUN: llc -run-pass none -o - %s 2>&1 | FileCheck %s +# RUN: llc -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser accepts files without the LLVM IR. --- diff --git a/llvm/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir b/llvm/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir index a5737c2c152..cf095537beb 100644 --- a/llvm/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir +++ b/llvm/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir @@ -1,4 +1,4 @@ -# RUN: llc -run-pass none -o - %s 2>&1 | FileCheck %s +# RUN: llc -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser preserves unnamed LLVM IR block # references. diff --git a/llvm/test/CodeGen/MIR/Generic/runPass.mir b/llvm/test/CodeGen/MIR/Generic/runPass.mir index bf37bdd1836..eeef9d52651 100644 --- a/llvm/test/CodeGen/MIR/Generic/runPass.mir +++ b/llvm/test/CodeGen/MIR/Generic/runPass.mir @@ -1,4 +1,4 @@ -# RUN: llc -run-pass=greedy -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s +# RUN: llc -run-pass=greedy -debug-pass=Arguments -o - %s | FileCheck %s # Check that passes are initialized correctly, so that it's possible to # use -run-pass. diff --git a/llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir b/llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir index 5e7dde26769..9847d027ee0 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s 2>&1 | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s --- | diff --git a/llvm/test/CodeGen/X86/implicit-use-spill.mir b/llvm/test/CodeGen/X86/implicit-use-spill.mir index 827f0f186ce..94bdd47b447 100644 --- a/llvm/test/CodeGen/X86/implicit-use-spill.mir +++ b/llvm/test/CodeGen/X86/implicit-use-spill.mir @@ -1,4 +1,4 @@ -# RUN: llc -run-pass=greedy -mtriple=x86_64-apple-macosx -o - %s 2>&1 | FileCheck %s +# RUN: llc -run-pass=greedy -mtriple=x86_64-apple-macosx -o - %s | FileCheck %s # Make sure we don't assert when we try to reload a value that is just implicitly used. --- |
