diff options
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td | 16 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsEVAInstrInfo.td | 6 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt | 2 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt | 2 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/micromips32r6/valid.s | 2 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/micromips64r6/valid.s | 2 |
7 files changed, 38 insertions, 2 deletions
diff --git a/llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td b/llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td index 400f6eef3fb..52d45ad9bd9 100644 --- a/llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td +++ b/llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td @@ -860,3 +860,13 @@ class POOL32F_CLASS_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct> let Inst{10-9} = fmt; let Inst{8-0} = funct; } + +class POOL32A_TLBINV_FM_MMR6<string instr_asm, bits<10> funct> + : MMR6Arch<instr_asm>, MipsR6Inst { + bits<32> Inst; + + let Inst{31-26} = 0x0; + let Inst{25-16} = 0x0; + let Inst{15-6} = funct; + let Inst{5-0} = 0b111100; +} diff --git a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td index da4da3f2310..4286c36e21c 100644 --- a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -168,6 +168,8 @@ class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>; class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>; class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6; class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>; +class TLBINV_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinv", 0x10d>; +class TLBINVF_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinvf", 0x14d>; class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd, RegisterOperand GPROpnd> @@ -924,6 +926,16 @@ class SWSP_MMR6_DESC let mayStore = 1; } +class TLBINV_MMR6_DESC_BASE<string opstr> { + dag OutOperandList = (outs); + dag InOperandList = (ins); + string AsmString = opstr; + list<dag> Pattern = []; +} + +class TLBINV_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinv">; +class TLBINVF_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinvf">; + //===----------------------------------------------------------------------===// // // Instruction Definitions @@ -1202,6 +1214,10 @@ def CLASS_S_MMR6 : StdMMR6Rel, CLASS_S_MMR6_ENC, CLASS_S_MMR6_DESC, ISA_MICROMIPS32R6; def CLASS_D_MMR6 : StdMMR6Rel, CLASS_D_MMR6_ENC, CLASS_D_MMR6_DESC, ISA_MICROMIPS32R6; +def TLBINV_MMR6 : StdMMR6Rel, TLBINV_MMR6_ENC, TLBINV_MMR6_DESC, + ISA_MICROMIPS32R6; +def TLBINVF_MMR6 : StdMMR6Rel, TLBINVF_MMR6_ENC, TLBINVF_MMR6_DESC, + ISA_MICROMIPS32R6; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Mips/MipsEVAInstrInfo.td b/llvm/lib/Target/Mips/MipsEVAInstrInfo.td index 36c9694cbad..130d5f29b30 100644 --- a/llvm/lib/Target/Mips/MipsEVAInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsEVAInstrInfo.td @@ -185,8 +185,10 @@ def LLE : LLE_ENC, LLE_DESC, INSN_EVA; def SCE : SCE_ENC, SCE_DESC, INSN_EVA; } -def TLBINV : TLBINV_ENC, TLBINV_DESC, INSN_EVA; -def TLBINVF : TLBINVF_ENC, TLBINVF_DESC, INSN_EVA; +let AdditionalPredicates = [NotInMicroMips] in { + def TLBINV : TLBINV_ENC, TLBINV_DESC, INSN_EVA; + def TLBINVF : TLBINVF_ENC, TLBINVF_DESC, INSN_EVA; +} def CACHEE : CACHEE_ENC, CACHEE_DESC, INSN_EVA; def PREFE : PREFE_ENC, PREFE_DESC, INSN_EVA; diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt index b8e69f833a0..87e103e8adf 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt @@ -256,3 +256,5 @@ 0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4 0x00 0x00 0x47 0x7c # CHECK: di 0x00 0x0f 0x47 0x7c # CHECK: di $15 +0x00 0x00 0x43 0x7c # CHECK: tlbinv +0x00 0x00 0x53 0x7c # CHECK: tlbinvf diff --git a/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt index 4f2325fe7ce..dd064fcae6a 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt @@ -169,3 +169,5 @@ 0x00 0x00 0xe3 0x7c # CHECK: deret 0x00 0x00 0x47 0x7c # CHECK: di 0x00 0x0f 0x47 0x7c # CHECK: di $15 +0x00 0x00 0x43 0x7c # CHECK: tlbinv +0x00 0x00 0x53 0x7c # CHECK: tlbinvf diff --git a/llvm/test/MC/Mips/micromips32r6/valid.s b/llvm/test/MC/Mips/micromips32r6/valid.s index 62048a91163..9cd217dbfa9 100644 --- a/llvm/test/MC/Mips/micromips32r6/valid.s +++ b/llvm/test/MC/Mips/micromips32r6/valid.s @@ -250,3 +250,5 @@ class.s $f2, $f3 # CHECK: class.s $f2, $f3 # encoding: [0x54,0x62,0x00,0x60] class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x60] deret # CHECK: deret # encoding: [0x00,0x00,0xe3,0x7c] + tlbinv # CHECK: tlbinv # encoding: [0x00,0x00,0x43,0x7c] + tlbinvf # CHECK: tlbinvf # encoding: [0x00,0x00,0x53,0x7c] diff --git a/llvm/test/MC/Mips/micromips64r6/valid.s b/llvm/test/MC/Mips/micromips64r6/valid.s index 649410eba1f..34befeeeb4a 100644 --- a/llvm/test/MC/Mips/micromips64r6/valid.s +++ b/llvm/test/MC/Mips/micromips64r6/valid.s @@ -154,5 +154,7 @@ a: ceil.l.d $f1, $f3 # CHECK: ceil.l.d $f1, $f3 # encoding: [0x54,0x23,0x53,0x3b] floor.l.s $f1, $f3 # CHECK: floor.l.s $f1, $f3 # encoding: [0x54,0x23,0x03,0x3b] floor.l.d $f1, $f3 # CHECK: floor.l.d $f1, $f3 # encoding: [0x54,0x23,0x43,0x3b] + tlbinv # CHECK: tlbinv # encoding: [0x00,0x00,0x43,0x7c] + tlbinvf # CHECK: tlbinvf # encoding: [0x00,0x00,0x53,0x7c] 1: |
