diff options
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 11 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrInfo.h | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/packetize-tailcall-arg.ll | 22 |
4 files changed, 35 insertions, 1 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index d3fd517fe49..f3230a76f25 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -2437,6 +2437,17 @@ bool HexagonInstrInfo::isSpillPredRegOp(const MachineInstr *MI) const { } +bool HexagonInstrInfo::isTailCall(const MachineInstr *MI) const { + if (!MI->isBranch()) + return false; + + for (auto &Op : MI->operands()) + if (Op.isGlobal() || Op.isSymbol()) + return true; + return false; +} + + // Returns true when SU has a timing class TC1. bool HexagonInstrInfo::isTC1(const MachineInstr *MI) const { unsigned SchedClass = MI->getDesc().getSchedClass(); diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h index 92f8c33f693..50bd7e9e845 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h @@ -309,6 +309,7 @@ public: bool isSignExtendingLoad(const MachineInstr &MI) const; bool isSolo(const MachineInstr* MI) const; bool isSpillPredRegOp(const MachineInstr *MI) const; + bool isTailCall(const MachineInstr *MI) const; bool isTC1(const MachineInstr *MI) const; bool isTC2(const MachineInstr *MI) const; bool isTC2Early(const MachineInstr *MI) const; diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index 033c02154db..0b3aea1bdbe 100644 --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -1248,7 +1248,7 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) { RC = HRI->getMinimalPhysRegClass(DepReg); } - if (I->isCall() || I->isReturn()) { + if (I->isCall() || I->isReturn() || HII->isTailCall(I)) { if (!isRegDependence(DepType)) continue; if (!isCallDependent(I, DepType, SUJ->Succs[i].getReg())) diff --git a/llvm/test/CodeGen/Hexagon/packetize-tailcall-arg.ll b/llvm/test/CodeGen/Hexagon/packetize-tailcall-arg.ll new file mode 100644 index 00000000000..17afd7df94a --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/packetize-tailcall-arg.ll @@ -0,0 +1,22 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; There should only be one packet: +; { +; jump free +; r0 = memw(r0 + #-4) +; } +; +; CHECK: { +; CHECK-NOT: { + +define void @fred(i8* %p) nounwind { +entry: + %arrayidx = getelementptr inbounds i8, i8* %p, i32 -4 + %t0 = bitcast i8* %arrayidx to i8** + %t1 = load i8*, i8** %t0, align 4 + tail call void @free(i8* %t1) + ret void +} + +; Function Attrs: nounwind +declare void @free(i8* nocapture) nounwind + |
