diff options
| -rw-r--r-- | llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 13 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsRegisterInfo.td | 19 |
2 files changed, 0 insertions, 32 deletions
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 927b15e916f..a7148f7156e 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -892,14 +892,6 @@ private: .getRegister(RegIdx.Index); } - /// Coerce the register to FGRH32 and return the real register for the current - /// target. - unsigned getFGRH32Reg() const { - assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!"); - return RegIdx.RegInfo->getRegClass(Mips::FGRH32RegClassID) - .getRegister(RegIdx.Index); - } - /// Coerce the register to FCC and return the real register for the current /// target. unsigned getFCCReg() const { @@ -1097,11 +1089,6 @@ public: "registers"); } - void addFGRH32AsmRegOperands(MCInst &Inst, unsigned N) const { - assert(N == 1 && "Invalid number of operands!"); - Inst.addOperand(MCOperand::createReg(getFGRH32Reg())); - } - void addFCCAsmRegOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createReg(getFCCReg())); diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.td b/llvm/lib/Target/Mips/MipsRegisterInfo.td index ed09054c590..7dca8835aad 100644 --- a/llvm/lib/Target/Mips/MipsRegisterInfo.td +++ b/llvm/lib/Target/Mips/MipsRegisterInfo.td @@ -391,16 +391,6 @@ def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)> { }]; } -def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>, - Unallocatable { - // Do not allocate odd registers when given -mattr=+nooddspreg. - let AltOrders = [(decimate FGRH32, 2)]; - let AltOrderSelect = [{ - const auto & S = MF.getSubtarget<MipsSubtarget>(); - return S.isABI_O32() && !S.useOddSPReg(); - }]; -} - def AFGR64 : RegisterClass<"Mips", [f64], 64, (add // Return Values and Arguments D0, D1, @@ -602,11 +592,6 @@ def StrictlyFGR32AsmOperand : MipsAsmRegOperand { let PredicateMethod = "isStrictlyFGRAsmReg"; } -def FGRH32AsmOperand : MipsAsmRegOperand { - let Name = "FGRH32AsmReg"; - let PredicateMethod = "isFGRAsmReg"; -} - def FCCRegsAsmOperand : MipsAsmRegOperand { let Name = "FCCAsmReg"; } @@ -714,10 +699,6 @@ def FGRCCOpnd : RegisterOperand<FGRCC> { let ParserMatchClass = FGR32AsmOperand; } -def FGRH32Opnd : RegisterOperand<FGRH32> { - let ParserMatchClass = FGRH32AsmOperand; -} - def FCCRegsOpnd : RegisterOperand<FCC> { let ParserMatchClass = FCCRegsAsmOperand; } |
