diff options
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/NVPTX/tid-range.ll | 18 |
2 files changed, 19 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index cb803585282..e98c851e2c7 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -7344,7 +7344,7 @@ SDValue SelectionDAGBuilder::lowerRangeToAssertZExt(SelectionDAG &DAG, return Op; Constant *Hi = cast<ConstantAsMetadata>(Range->getOperand(1))->getValue(); - unsigned Bits = cast<ConstantInt>(Hi)->getValue().logBase2(); + unsigned Bits = cast<ConstantInt>(Hi)->getValue().ceilLogBase2(); EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), Bits); diff --git a/llvm/test/CodeGen/NVPTX/tid-range.ll b/llvm/test/CodeGen/NVPTX/tid-range.ll new file mode 100644 index 00000000000..3dc4008810a --- /dev/null +++ b/llvm/test/CodeGen/NVPTX/tid-range.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -march=nvptx64 | FileCheck %s +declare i32 @get_register() + +define i1 @test1() { +entry: + %call = call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !range !0 + %cmp = icmp eq i32 %call, 1 + ret i1 %cmp +} + +; CHECK-LABEL: test1( +; CHECK: setp.eq.s32 %p1, %r1, 1; +; CHECK: selp.u32 %[[R:.+]], 1, 0, %p1; +; CHECK: st.param.b32 [func_retval0+0], %[[R]]; + +declare i32 @llvm.nvvm.read.ptx.sreg.tid.x() + +!0 = !{ i32 0, i32 3 } |
