diff options
| -rw-r--r-- | llvm/include/llvm/Target/TargetLowering.h | 7 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 54 |
2 files changed, 25 insertions, 36 deletions
diff --git a/llvm/include/llvm/Target/TargetLowering.h b/llvm/include/llvm/Target/TargetLowering.h index ba77a88e9d7..4ec80a5a3eb 100644 --- a/llvm/include/llvm/Target/TargetLowering.h +++ b/llvm/include/llvm/Target/TargetLowering.h @@ -1422,6 +1422,13 @@ protected: PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; } + /// Convenience method to set an operation to Promote and specify the type + /// in a single call. + void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { + setOperationAction(Opc, OrigVT, Promote); + AddPromotedToType(Opc, OrigVT, DestVT); + } + /// Targets should invoke this method for each target independent node that /// they want to provide a custom DAG combiner for by implementing the /// PerformDAGCombine virtual method. diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 61e48468a49..7f699762262 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -324,10 +324,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, // Promote the i8 variants and force them on up to i32 which has a shorter // encoding. - setOperationAction(ISD::CTTZ , MVT::i8 , Promote); - AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32); - setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote); - AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32); + setOperationPromotedToType(ISD::CTTZ , MVT::i8 , MVT::i32); + setOperationPromotedToType(ISD::CTTZ_ZERO_UNDEF, MVT::i8 , MVT::i32); if (Subtarget.hasBMI()) { setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand); setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand); @@ -343,10 +341,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, if (Subtarget.hasLZCNT()) { // When promoting the i8 variants, force them to i32 for a shorter // encoding. - setOperationAction(ISD::CTLZ , MVT::i8 , Promote); - AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32); - setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote); - AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32); + setOperationPromotedToType(ISD::CTLZ , MVT::i8 , MVT::i32); + setOperationPromotedToType(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32); setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand); setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand); if (Subtarget.is64Bit()) @@ -885,16 +881,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) { - setOperationAction(ISD::AND, VT, Promote); - AddPromotedToType (ISD::AND, VT, MVT::v2i64); - setOperationAction(ISD::OR, VT, Promote); - AddPromotedToType (ISD::OR, VT, MVT::v2i64); - setOperationAction(ISD::XOR, VT, Promote); - AddPromotedToType (ISD::XOR, VT, MVT::v2i64); - setOperationAction(ISD::LOAD, VT, Promote); - AddPromotedToType (ISD::LOAD, VT, MVT::v2i64); - setOperationAction(ISD::SELECT, VT, Promote); - AddPromotedToType (ISD::SELECT, VT, MVT::v2i64); + setOperationPromotedToType(ISD::AND, VT, MVT::v2i64); + setOperationPromotedToType(ISD::OR, VT, MVT::v2i64); + setOperationPromotedToType(ISD::XOR, VT, MVT::v2i64); + setOperationPromotedToType(ISD::LOAD, VT, MVT::v2i64); + setOperationPromotedToType(ISD::SELECT, VT, MVT::v2i64); } // Custom lower v2i64 and v2f64 selects. @@ -1203,16 +1194,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64. for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) { - setOperationAction(ISD::AND, VT, Promote); - AddPromotedToType (ISD::AND, VT, MVT::v4i64); - setOperationAction(ISD::OR, VT, Promote); - AddPromotedToType (ISD::OR, VT, MVT::v4i64); - setOperationAction(ISD::XOR, VT, Promote); - AddPromotedToType (ISD::XOR, VT, MVT::v4i64); - setOperationAction(ISD::LOAD, VT, Promote); - AddPromotedToType (ISD::LOAD, VT, MVT::v4i64); - setOperationAction(ISD::SELECT, VT, Promote); - AddPromotedToType (ISD::SELECT, VT, MVT::v4i64); + setOperationPromotedToType(ISD::AND, VT, MVT::v4i64); + setOperationPromotedToType(ISD::OR, VT, MVT::v4i64); + setOperationPromotedToType(ISD::XOR, VT, MVT::v4i64); + setOperationPromotedToType(ISD::LOAD, VT, MVT::v4i64); + setOperationPromotedToType(ISD::SELECT, VT, MVT::v4i64); } } @@ -1496,8 +1482,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, } } for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) { - setOperationAction(ISD::SELECT, VT, Promote); - AddPromotedToType (ISD::SELECT, VT, MVT::v8i64); + setOperationPromotedToType(ISD::SELECT, VT, MVT::v8i64); } }// has AVX-512 @@ -1592,12 +1577,9 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(ISD::MLOAD, VT, Legal); setOperationAction(ISD::MSTORE, VT, Legal); - setOperationAction(ISD::AND, VT, Promote); - AddPromotedToType (ISD::AND, VT, MVT::v8i64); - setOperationAction(ISD::OR, VT, Promote); - AddPromotedToType (ISD::OR, VT, MVT::v8i64); - setOperationAction(ISD::XOR, VT, Promote); - AddPromotedToType (ISD::XOR, VT, MVT::v8i64); + setOperationPromotedToType(ISD::AND, VT, MVT::v8i64); + setOperationPromotedToType(ISD::OR, VT, MVT::v8i64); + setOperationPromotedToType(ISD::XOR, VT, MVT::v8i64); } } |
