diff options
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir b/llvm/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir index 4a4a5e143ee..f3d105f75da 100644 --- a/llvm/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir +++ b/llvm/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass expand-condsets -o - %s -verify-machineinstrs -debug-only=expand-condsets | FileCheck %s +# RUN: llc -march=hexagon -run-pass expand-condsets -o - %s -verify-machineinstrs -debug-only=expand-condsets 2>&1 | FileCheck %s # REQUIRES: asserts # Check that coalesced registers are removed from live intervals. |
