diff options
9 files changed, 168 insertions, 72 deletions
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index 34d4c57858a..479c9e7eeae 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -902,6 +902,14 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) { report("Non-generic instruction cannot have a type", MI); } + // Generic opcodes must not have physical register operands. + if (isPreISelGenericOpcode(MCID.getOpcode())) { + for (auto &Op : MI->operands()) { + if (Op.isReg() && TargetRegisterInfo::isPhysicalRegister(Op.getReg())) + report("Generic instruction cannot have physical register", MI); + } + } + StringRef ErrorInfo; if (!TII->verifyInstruction(*MI, ErrorInfo)) report(ErrorInfo.data(), MI); diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir index 2a22a036397..cc25cc378fb 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir @@ -64,15 +64,19 @@ # Based on the type i32, this should be gpr. name: defaultMapping legalized: true +# CHECK-LABEL: name: defaultMapping # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr } +# CHECK: - { id: 0, class: gpr } +# CHECK: - { id: 1, class: gpr } registers: - { id: 0, class: _ } + - { id: 1, class: _ } body: | bb.0.entry: liveins: %x0 - ; CHECK: %0(32) = G_ADD s32 %w0 - %0(32) = G_ADD s32 %w0, %w0 + ; CHECK: %1(32) = G_ADD s32 %0 + %0(32) = COPY %w0 + %1(32) = G_ADD s32 %0, %0 ... --- @@ -81,15 +85,20 @@ body: | # FPR is used for both floating point and vector registers. name: defaultMappingVector legalized: true +# CHECK-LABEL: name: defaultMappingVector # CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr } +# CHECK: - { id: 0, class: fpr } +# CHECK: - { id: 1, class: fpr } registers: - { id: 0, class: _ } + - { id: 1, class: _ } body: | bb.0.entry: liveins: %d0 - ; CHECK: %0(64) = G_ADD <2 x s32> %d0 - %0(64) = G_ADD <2 x s32> %d0, %d0 + ; CHECK: %0(64) = COPY %d0 + ; CHECK: %1(64) = G_ADD <2 x s32> %0 + %0(64) = COPY %d0 + %1(64) = G_ADD <2 x s32> %0, %0 ... --- @@ -98,26 +107,32 @@ body: | # in FPR, but at the use, it should be GPR. name: defaultMapping1Repair legalized: true +# CHECK-LABEL: name: defaultMapping1Repair # CHECK: registers: # CHECK-NEXT: - { id: 0, class: fpr } # CHECK-NEXT: - { id: 1, class: gpr } # CHECK-NEXT: - { id: 2, class: gpr } +# CHECK-NEXT: - { id: 3, class: gpr } registers: - { id: 0, class: _ } - { id: 1, class: _ } + - { id: 2, class: _ } body: | bb.0.entry: liveins: %s0, %x0 ; CHECK: %0(32) = COPY %s0 - ; CHECK-NEXT: %2(32) = COPY %0 - ; CHECK-NEXT: %1(32) = G_ADD s32 %2, %w0 + ; CHECK-NEXT: %1(32) = COPY %w0 + ; CHECK-NEXT: %3(32) = COPY %0 + ; CHECK-NEXT: %2(32) = G_ADD s32 %3, %1 %0(32) = COPY %s0 - %1(32) = G_ADD s32 %0, %w0 + %1(32) = COPY %w0 + %2(32) = G_ADD s32 %0, %1 ... # Check that we repair the assignment for %0 differently for both uses. name: defaultMapping2Repairs legalized: true +# CHECK-LABEL: name: defaultMapping2Repairs # CHECK: registers: # CHECK-NEXT: - { id: 0, class: fpr } # CHECK-NEXT: - { id: 1, class: gpr } @@ -144,6 +159,7 @@ body: | # fixes that. name: defaultMappingDefRepair legalized: true +# CHECK-LABEL: name: defaultMappingDefRepair # CHECK: registers: # CHECK-NEXT: - { id: 0, class: gpr } # CHECK-NEXT: - { id: 1, class: fpr } @@ -155,10 +171,10 @@ body: | bb.0.entry: liveins: %w0 ; CHECK: %0(32) = COPY %w0 - ; CHECK-NEXT: %2(32) = G_ADD s32 %0, %w0 + ; CHECK-NEXT: %2(32) = G_ADD s32 %0, %0 ; CHECK-NEXT: %1(32) = COPY %2 %0(32) = COPY %w0 - %1(32) = G_ADD s32 %0, %w0 + %1(32) = G_ADD s32 %0, %0 ... --- @@ -182,16 +198,16 @@ body: | bb.0.entry: successors: %bb.2.end, %bb.1.then liveins: %x0, %x1, %w2 - + %0 = LDRWui killed %x0, 0 :: (load 4 from %ir.src) %1 = COPY %x1 %2 = COPY %w2 TBNZW killed %2, 0, %bb.2.end - + bb.1.then: successors: %bb.2.end %3(32) = G_ADD s32 %0, %0 - + bb.2.end: %4(32) = PHI %0, %bb.0.entry, %3, %bb.1.then STRWui killed %4, killed %1, 0 :: (store 4 into %ir.dst) @@ -202,32 +218,39 @@ body: | # Make sure we can repair physical register uses as well. name: defaultMappingUseRepairPhysReg legalized: true +# CHECK-LABEL: name: defaultMappingUseRepairPhysReg # CHECK: registers: # CHECK-NEXT: - { id: 0, class: gpr } -# CHECK-NEXT: - { id: 1, class: gpr } +# CHECK-NEXT: - { id: 1, class: fpr } # CHECK-NEXT: - { id: 2, class: gpr } +# CHECK-NEXT: - { id: 3, class: gpr } registers: - { id: 0, class: _ } - { id: 1, class: _ } + - { id: 2, class: _ } body: | bb.0.entry: liveins: %w0, %s0 ; CHECK: %0(32) = COPY %w0 - ; CHECK-NEXT: %2(32) = COPY %s0 - ; CHECK-NEXT: %1(32) = G_ADD s32 %0, %2 + ; CHECK-NEXT: %1(32) = COPY %s0 + ; CHECK-NEXT: %3(32) = COPY %1 + ; CHECK-NEXT: %2(32) = G_ADD s32 %0, %3 %0(32) = COPY %w0 - %1(32) = G_ADD s32 %0, %s0 + %1(32) = COPY %s0 + %2(32) = G_ADD s32 %0, %1 ... --- # Make sure we can repair physical register defs. name: defaultMappingDefRepairPhysReg legalized: true +# CHECK-LABEL: name: defaultMappingDefRepairPhysReg # CHECK: registers: # CHECK-NEXT: - { id: 0, class: gpr } # CHECK-NEXT: - { id: 1, class: gpr } registers: - { id: 0, class: _ } + - { id: 1, class: _ } body: | bb.0.entry: liveins: %w0 @@ -235,7 +258,8 @@ body: | ; CHECK-NEXT: %1(32) = G_ADD s32 %0, %0 ; CHECK-NEXT: %s0 = COPY %1 %0(32) = COPY %w0 - %s0 = G_ADD s32 %0, %0 + %1(32) = G_ADD s32 %0, %0 + %s0 = COPY %1 ... --- @@ -243,6 +267,7 @@ body: | # G_OR instruction from fpr to gpr. name: greedyMappingOr legalized: true +# CHECK-LABEL: name: greedyMappingOr # CHECK: registers: # CHECK-NEXT: - { id: 0, class: gpr } # CHECK-NEXT: - { id: 1, class: gpr } @@ -289,6 +314,7 @@ body: | # %2 constraint. name: greedyMappingOrWithConstraints legalized: true +# CHECK-LABEL: name: greedyMappingOrWithConstraints # CHECK: registers: # CHECK-NEXT: - { id: 0, class: gpr } # CHECK-NEXT: - { id: 1, class: gpr } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir index 18d38a3a448..d1d959976d8 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir @@ -23,22 +23,34 @@ registers: - { id: 0, class: _ } - { id: 1, class: _ } - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } + - { id: 8, class: _ } body: | bb.0.entry: liveins: %x0, %x1, %x2, %x3 ; CHECK-LABEL: name: test_scalar_add_big - ; CHECK-DAG: [[LHS_LO:%.*]](64), [[LHS_HI:%.*]](64) = G_EXTRACT { s64, s64, s128 } %0, 0, 64 - ; CHECK-DAG: [[RHS_LO:%.*]](64), [[RHS_HI:%.*]](64) = G_EXTRACT { s64, s64, s128 } %1, 0, 64 + ; CHECK-DAG: [[LHS_LO:%.*]](64), [[LHS_HI:%.*]](64) = G_EXTRACT { s64, s64, s128 } %4, 0, 64 + ; CHECK-DAG: [[RHS_LO:%.*]](64), [[RHS_HI:%.*]](64) = G_EXTRACT { s64, s64, s128 } %5, 0, 64 ; CHECK-DAG: [[CARRY0_32:%.*]](32) = G_CONSTANT s32 0 ; CHECK-DAG: [[CARRY0:%[0-9]+]](1) = G_TRUNC { s1, s32 } [[CARRY0_32]] ; CHECK: [[RES_LO:%.*]](64), [[CARRY:%.*]](1) = G_UADDE s64 [[LHS_LO]], [[RHS_LO]], [[CARRY0]] ; CHECK: [[RES_HI:%.*]](64), {{%.*}}(1) = G_UADDE s64 [[LHS_HI]], [[RHS_HI]], [[CARRY]] - ; CHECK: %2(128) = G_SEQUENCE { s128, s64, s64 } [[RES_LO]], 0, [[RES_HI]], 64 + ; CHECK: %6(128) = G_SEQUENCE { s128, s64, s64 } [[RES_LO]], 0, [[RES_HI]], 64 - %0(128) = G_SEQUENCE { s128, s64, s64 } %x0, 0, %x1, 64 - %1(128) = G_SEQUENCE { s128, s64, s64 } %x2, 0, %x3, 64 - %2(128) = G_ADD s128 %0, %1 - %x0, %x1 = G_EXTRACT { s64, s64, s128 } %2, 0, 64 + %0(64) = COPY %x0 + %1(64) = COPY %x1 + %2(64) = COPY %x2 + %3(64) = COPY %x3 + %4(128) = G_SEQUENCE { s128, s64, s64 } %0, 0, %1, 64 + %5(128) = G_SEQUENCE { s128, s64, s64 } %2, 0, %3, 64 + %6(128) = G_ADD s128 %4, %5 + %7(64), %8(64) = G_EXTRACT { s64, s64, s128 } %6, 0, 64 + %x0 = COPY %7 + %x1 = COPY %8 ... --- @@ -47,16 +59,22 @@ registers: - { id: 0, class: _ } - { id: 1, class: _ } - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } body: | bb.0.entry: liveins: %x0, %x1, %x2, %x3 ; CHECK-LABEL: name: test_scalar_add_small - ; CHECK: [[RES:%.*]](8) = G_ADD s8 %0, %1 + ; CHECK: [[RES:%.*]](8) = G_ADD s8 %2, %3 - %0(8) = G_TRUNC { s8, s64 } %x0 - %1(8) = G_TRUNC { s8, s64 } %x1 - %2(8) = G_ADD s8 %0, %1 - %x0 = G_ANYEXT { s64, s8 } %2 + %0(64) = COPY %x0 + %1(64) = COPY %x1 + %2(8) = G_TRUNC { s8, s64 } %0 + %3(8) = G_TRUNC { s8, s64 } %1 + %4(8) = G_ADD s8 %2, %3 + %5(64) = G_ANYEXT { s64, s8 } %4 + %x0 = COPY %5 ... --- @@ -65,18 +83,30 @@ registers: - { id: 0, class: _ } - { id: 1, class: _ } - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } + - { id: 8, class: _ } body: | bb.0.entry: liveins: %q0, %q1, %q2, %q3 ; CHECK-LABEL: name: test_vector_add - ; CHECK-DAG: [[LHS_LO:%.*]](128), [[LHS_HI:%.*]](128) = G_EXTRACT { s128, s128, s256 } %0, 0, 128 - ; CHECK-DAG: [[RHS_LO:%.*]](128), [[RHS_HI:%.*]](128) = G_EXTRACT { s128, s128, s256 } %1, 0, 128 + ; CHECK-DAG: [[LHS_LO:%.*]](128), [[LHS_HI:%.*]](128) = G_EXTRACT { s128, s128, s256 } %4, 0, 128 + ; CHECK-DAG: [[RHS_LO:%.*]](128), [[RHS_HI:%.*]](128) = G_EXTRACT { s128, s128, s256 } %5, 0, 128 ; CHECK: [[RES_LO:%.*]](128) = G_ADD <2 x s64> [[LHS_LO]], [[RHS_LO]] ; CHECK: [[RES_HI:%.*]](128) = G_ADD <2 x s64> [[LHS_HI]], [[RHS_HI]] - ; CHECK: %2(256) = G_SEQUENCE { s256, s128, s128 } [[RES_LO]], 0, [[RES_HI]], 128 + ; CHECK: %6(256) = G_SEQUENCE { s256, s128, s128 } [[RES_LO]], 0, [[RES_HI]], 128 - %0(256) = G_SEQUENCE { s256, s128, s128 } %q0, 0, %q1, 128 - %1(256) = G_SEQUENCE { s256, s128, s128 } %q2, 0, %q3, 128 - %2(256) = G_ADD <4 x s64> %0, %1 - %q0, %q1 = G_EXTRACT { s128, s128, s256 } %2, 0, 128 + %0(128) = COPY %q0 + %1(128) = COPY %q1 + %2(128) = COPY %q2 + %3(128) = COPY %q3 + %4(256) = G_SEQUENCE { s256, s128, s128 } %0, 0, %1, 128 + %5(256) = G_SEQUENCE { s256, s128, s128 } %2, 0, %3, 128 + %6(256) = G_ADD <4 x s64> %4, %5 + %7(128), %8(128) = G_EXTRACT { s128, s128, s256 } %6, 0, 128 + %q0 = COPY %7 + %q1 = COPY %8 ... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir index 5a2c59b3a2c..e55fa9b241e 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir @@ -15,14 +15,20 @@ registers: - { id: 0, class: _ } - { id: 1, class: _ } - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } body: | bb.0.entry: liveins: %x0, %x1, %x2, %x3 ; CHECK-LABEL: name: test_scalar_and_small - ; CHECK: [[RES:%.*]](8) = G_AND s8 %0, %1 + ; CHECK: %4(8) = G_AND s8 %2, %3 - %0(8) = G_TRUNC { s8, s32 } %x0 - %1(8) = G_TRUNC { s8, s32 } %x1 - %2(8) = G_AND s8 %0, %1 - %x0 = G_ANYEXT { s64, s8 } %2 + %0(64) = COPY %x0 + %1(64) = COPY %x1 + %2(8) = G_TRUNC { s8, s64 } %0 + %3(8) = G_TRUNC { s8, s64 } %1 + %4(8) = G_AND s8 %2, %3 + %5(64) = G_ANYEXT { s64, s8 } %2 + %x0 = COPY %5 ... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir index 30991ac8c95..02df8537d7c 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir @@ -15,14 +15,20 @@ registers: - { id: 0, class: _ } - { id: 1, class: _ } - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } body: | bb.0.entry: liveins: %x0, %x1, %x2, %x3 ; CHECK-LABEL: name: test_scalar_mul_small - ; CHECK: [[RES:%.*]](8) = G_MUL s8 %0, %1 + ; CHECK: %4(8) = G_MUL s8 %2, %3 - %0(8) = G_TRUNC { s8, s64 } %x0 - %1(8) = G_TRUNC { s8, s64 } %x1 - %2(8) = G_MUL s8 %0, %1 - %x0 = G_ANYEXT { s64, s8 } %2 + %0(64) = COPY %x0 + %1(64) = COPY %x1 + %2(8) = G_TRUNC { s8, s64 } %0 + %3(8) = G_TRUNC { s8, s64 } %1 + %4(8) = G_MUL s8 %2, %3 + %5(64) = G_ANYEXT { s64, s8 } %2 + %x0 = COPY %5 ... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir index 3564b3b3b58..f71858614b2 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir @@ -15,14 +15,20 @@ registers: - { id: 0, class: _ } - { id: 1, class: _ } - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } body: | bb.0.entry: liveins: %x0, %x1, %x2, %x3 ; CHECK-LABEL: name: test_scalar_or_small - ; CHECK: %2(8) = G_OR s8 %0, %1 + ; CHECK: %4(8) = G_OR s8 %2, %3 - %0(8) = G_TRUNC { s8, s64 } %x0 - %1(8) = G_TRUNC { s8, s64 } %x1 - %2(8) = G_OR s8 %0, %1 - %x0 = G_ANYEXT { s64, s8 } %2 + %0(64) = COPY %x0 + %1(64) = COPY %x1 + %2(8) = G_TRUNC { s8, s64 } %0 + %3(8) = G_TRUNC { s8, s64 } %1 + %4(8) = G_OR s8 %2, %3 + %5(64) = G_ANYEXT { s64, s8 } %2 + %x0 = COPY %5 ... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir index ec35e02315d..e0ab862262f 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir @@ -15,14 +15,20 @@ registers: - { id: 0, class: _ } - { id: 1, class: _ } - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } body: | bb.0.entry: liveins: %x0, %x1, %x2, %x3 ; CHECK-LABEL: name: test_scalar_sub_small ; CHECK: [[RES:%.*]](8) = G_SUB s8 %0, %1 - %0(8) = G_TRUNC { s8, s64 } %x0 - %1(8) = G_TRUNC { s8, s64 } %x1 - %2(8) = G_SUB s8 %0, %1 - %x0 = G_ANYEXT { s64, s8 } %2 + %0(64) = COPY %x0 + %1(64) = COPY %x1 + %2(8) = G_TRUNC { s8, s64 } %0 + %3(8) = G_TRUNC { s8, s64 } %1 + %4(8) = G_SUB s8 %0, %1 + %5(64) = G_ANYEXT { s64, s8 } %2 + %x0 = COPY %5 ... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir index b1e6d5a37b5..935279c7d52 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir @@ -15,14 +15,20 @@ registers: - { id: 0, class: _ } - { id: 1, class: _ } - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } body: | bb.0.entry: liveins: %x0, %x1, %x2, %x3 ; CHECK-LABEL: name: test_scalar_xor_small - ; CHECK: %2(8) = G_XOR s8 %0, %1 + ; CHECK: %4(8) = G_XOR s8 %2, %3 - %0(8) = G_TRUNC { s8, s64 } %x0 - %1(8) = G_TRUNC { s8, s64 } %x1 - %2(8) = G_XOR s8 %0, %1 - %x0 = G_ANYEXT { s64, s8 } %2 + %0(64) = COPY %x0 + %1(64) = COPY %x1 + %2(8) = G_TRUNC { s8, s64 } %0 + %3(8) = G_TRUNC { s8, s64 } %1 + %4(8) = G_XOR s8 %2, %3 + %5(64) = G_ANYEXT { s64, s8 } %2 + %x0 = COPY %5 ... diff --git a/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir b/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir index aad0a77261e..1554d710ec3 100644 --- a/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir +++ b/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir @@ -30,21 +30,23 @@ registers: - { id: 2, class: _ } - { id: 3, class: _ } - { id: 4, class: _ } + - { id: 5, class: _ } body: | bb.0: liveins: %edi - ; CHECK: %0(32) = G_ADD s32 %edi - %0(32) = G_ADD s32 %edi, %edi - ; CHECK: %1(64) = G_ADD <2 x s32> %edi - %1(64) = G_ADD <2 x s32> %edi, %edi - ; CHECK: %2(64) = G_ADD s64 %edi - %2(64) = G_ADD s64 %edi, %edi + ; CHECK: %1(32) = G_ADD s32 %0 + %0(32) = COPY %edi + %1(32) = G_ADD s32 %0, %0 + ; CHECK: %2(64) = G_ADD <2 x s32> %0 + %2(64) = G_ADD <2 x s32> %0, %0 + ; CHECK: %3(64) = G_ADD s64 %0 + %3(64) = G_ADD s64 %0, %0 ; G_ADD is actually not a valid operand for structure type, ; but that is the only one we have for now for testing. - ; CHECK: %3(64) = G_ADD s64 %edi - %3(64) = G_ADD s64 %edi, %edi - ; CHECK: %4(48) = G_ADD s48 %edi - %4(48) = G_ADD s48 %edi, %edi + ; CHECK: %4(64) = G_ADD s64 %0 + %4(64) = G_ADD s64 %0, %0 + ; CHECK: %5(48) = G_ADD s48 %0 + %5(48) = G_ADD s48 %0, %0 ... --- |
