diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64.td | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrInfo.td | 12 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64Subtarget.h | 2 | ||||
| -rw-r--r-- | llvm/test/MC/AArch64/armv8.5a-specctrl.s | 11 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/AArch64/armv8.5a-specctrl.txt | 9 |
5 files changed, 37 insertions, 2 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index 67b475de65a..79bae03b4b8 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -211,6 +211,9 @@ def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true", "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to " "an integer (in FP format) forcing it to fit into a 32- or 64-bit int" >; +def FeatureSpecCtrl : SubtargetFeature<"specctrl", "HasSpecCtrl", "true", + "Enable speculation control barrier" >; + //===----------------------------------------------------------------------===// // Architectures. // @@ -229,7 +232,7 @@ def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", def HasV8_5aOps : SubtargetFeature< "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions", - [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264] + [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecCtrl] >; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index d1daf6d7f76..310c1b60bf7 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -66,6 +66,8 @@ def HasAltNZCV : Predicate<"Subtarget->hasAlternativeNZCV()">, AssemblerPredicate<"FeatureAltFPCmp", "altnzcv">; def HasFRInt3264 : Predicate<"Subtarget->hasFRInt3264()">, AssemblerPredicate<"FeatureFRInt3264", "frint3264">; +def HasSpecCtrl : Predicate<"Subtarget->hasSpecCtrl()">, + AssemblerPredicate<"FeatureSpecCtrl", "specctrl">; def IsLE : Predicate<"Subtarget->isLittleEndian()">; def IsBE : Predicate<"!Subtarget->isLittleEndian()">; def UseAlternateSExtLoadCVTF32 @@ -627,9 +629,17 @@ def AXFLAG : PstateWriteSimple<(ins), "axflag", "">, Sched<[WriteSys]> { let Unpredictable{11-8} = 0b1111; let Inst{7-5} = 0b010; } - } // HasAltNZCV + +// Armv8.5-A speculation barrier +def SB : SimpleSystemI<0, (ins), "sb", "">, Sched<[]> { + let Inst{20-5} = 0b0001100110000111; + let Unpredictable{11-8} = 0b1111; + let Predicates = [HasSpecCtrl]; + let hasSideEffects = 1; +} + def : InstAlias<"clrex", (CLREX 0xf)>; def : InstAlias<"isb", (ISB 0xf)>; diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h index fec338c1ab3..8df6e5a6570 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.h +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -97,6 +97,7 @@ protected: // Armv8.5-A Extensions bool HasAlternativeNZCV = false; bool HasFRInt3264 = false; + bool HasSpecCtrl = false; // HasZeroCycleRegMove - Has zero-cycle register mov instructions. bool HasZeroCycleRegMove = false; @@ -312,6 +313,7 @@ public: bool hasAggressiveFMA() const { return HasAggressiveFMA; } bool hasAlternativeNZCV() const { return HasAlternativeNZCV; } bool hasFRInt3264() const { return HasFRInt3264; } + bool hasSpecCtrl() { return HasSpecCtrl; } bool isLittleEndian() const { return IsLittle; } diff --git a/llvm/test/MC/AArch64/armv8.5a-specctrl.s b/llvm/test/MC/AArch64/armv8.5a-specctrl.s new file mode 100644 index 00000000000..279a396250c --- /dev/null +++ b/llvm/test/MC/AArch64/armv8.5a-specctrl.s @@ -0,0 +1,11 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+specctrl < %s | FileCheck %s +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.5a < %s | FileCheck %s +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-specctrl < %s 2>&1 | FileCheck %s --check-prefix=NOSB + +// Flag manipulation +sb + +// CHECK: sb // encoding: [0xff,0x30,0x03,0xd5] + +// NOSB: instruction requires: specctrl +// NOSB-NEXT: sb diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.5a-specctrl.txt b/llvm/test/MC/Disassembler/AArch64/armv8.5a-specctrl.txt new file mode 100644 index 00000000000..d2174ae1dc1 --- /dev/null +++ b/llvm/test/MC/Disassembler/AArch64/armv8.5a-specctrl.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+specctrl -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+v8.5a -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=-specctrl -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB + +# New reg +0xff 0x30 0x03 0xd5 + +# CHECK: sb +# NOSB: msr S0_3_C3_C0_7, xzr |
