diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 9 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir | 31 |
2 files changed, 40 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index b4ea462959a..59b4712cfa9 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -308,6 +308,15 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); break; } + case AMDGPU::G_EXTRACT: { + unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI); + unsigned DstSize = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); + unsigned SrcSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI); + OpdsMapping[0] = AMDGPU::getValueMapping(BankID, DstSize); + OpdsMapping[1] = AMDGPU::getValueMapping(BankID, SrcSize); + OpdsMapping[2] = nullptr; + break; + } case AMDGPU::G_BITCAST: { unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI); diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir new file mode 100644 index 00000000000..550d38cfe9f --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir @@ -0,0 +1,31 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s + +--- +name: extract_lo32_i64_s +legalized: true + +body: | + bb.0: + liveins: $sgpr0_sgpr1 + ; CHECK-LABEL: name: extract_lo32_i64_s + ; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 + ; CHECK: [[EXTRACT:%[0-9]+]]:sgpr(s32) = G_EXTRACT [[COPY]](s64), 0 + %0:_(s64) = COPY $sgpr0_sgpr1 + %1:_(s32) = G_EXTRACT %0, 0 +... + +--- +name: extract_lo32_i64_v +legalized: true + +body: | + bb.0: + liveins: $vgpr0_vgpr1 + ; CHECK-LABEL: name: extract_lo32_i64_v + ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 + ; CHECK: [[EXTRACT:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s64), 0 + %0:_(s64) = COPY $vgpr0_vgpr1 + %1:_(s32) = G_EXTRACT %0, 0 +... |
