diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/calling-conventions.ll | 35 |
2 files changed, 33 insertions, 8 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td b/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td index 47dfa499206..6b9ebcfe0b7 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td @@ -17,7 +17,7 @@ class CCIfNotInReg<CCAction A> : CCIf<"!ArgFlags.isInReg()", A> {} // Calling convention for SI def CC_SI : CallingConv<[ - CCIfInReg<CCIfType<[f32, i32] , CCAssignToReg<[ + CCIfInReg<CCIfType<[f32, i32, f16] , CCAssignToReg<[ SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7, SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15, SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23, @@ -35,7 +35,7 @@ def CC_SI : CallingConv<[ >>>, // 32*4 + 4 is the minimum for a fetch shader consumer with 32 inputs. - CCIfNotInReg<CCIfType<[f32, i32] , CCAssignToReg<[ + CCIfNotInReg<CCIfType<[f32, i32, f16] , CCAssignToReg<[ VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7, VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15, VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23, @@ -76,7 +76,7 @@ def RetCC_SI : CallingConv<[ ]>>, // 32*4 + 4 is the minimum for a fetch shader with 32 outputs. - CCIfType<[f32] , CCAssignToReg<[ + CCIfType<[f32, f16] , CCAssignToReg<[ VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7, VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15, VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23, diff --git a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll index 57adc8be6a9..55c2b503430 100644 --- a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll +++ b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll @@ -1,9 +1,10 @@ -; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; Make sure we don't crash or assert on spir_kernel calling convention. -; SI-LABEL: {{^}}kernel: -; SI: s_endpgm +; GCN-LABEL: {{^}}kernel: +; GCN: s_endpgm define spir_kernel void @kernel(i32 addrspace(1)* %out) { entry: store i32 0, i32 addrspace(1)* %out @@ -11,10 +12,34 @@ entry: } ; FIXME: This is treated like a kernel -; SI-LABEL: {{^}}func: -; SI: s_endpgm +; GCN-LABEL: {{^}}func: +; GCN: s_endpgm define spir_func void @func(i32 addrspace(1)* %out) { entry: store i32 0, i32 addrspace(1)* %out ret void } + +; GCN-LABEL: {{^}}ps_ret_cc_f16: +; SI: v_cvt_f16_f32_e32 v0, v0 +; SI: v_cvt_f32_f16_e32 v0, v0 +; SI: v_add_f32_e32 v0, 1.0, v0 + +; VI: v_add_f16_e32 v0, 1.0, v0 +; VI: ; return +define amdgpu_ps half @ps_ret_cc_f16(half %arg0) { + %add = fadd half %arg0, 1.0 + ret half %add +} + +; GCN-LABEL: {{^}}ps_ret_cc_inreg_f16: +; SI: v_cvt_f16_f32_e32 v0, s0 +; SI: v_cvt_f32_f16_e32 v0, v0 +; SI: v_add_f32_e32 v0, 1.0, v0 + +; VI: v_add_f16_e64 v0, s0, 1.0 +; VI: ; return +define amdgpu_ps half @ps_ret_cc_inreg_f16(half inreg %arg0) { + %add = fadd half %arg0, 1.0 + ret half %add +} |
