diff options
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 15 | ||||
| -rw-r--r-- | llvm/test/CodeGen/MSP430/shift-amount-threshold-b.ll | 39 |
2 files changed, 17 insertions, 37 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index f42581da82d..96894613b4a 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -3655,11 +3655,13 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, const APInt &AndRHSC = AndRHS->getAPIntValue(); if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) { unsigned ShiftBits = AndRHSC.countTrailingZeros(); - SDValue Shift = DAG.getNode(ISD::SRL, dl, ShValTy, N0.getOperand(0), - DAG.getConstant(ShiftBits, dl, - ShiftTy)); - SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, ShValTy); - return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond); + if (ShiftBits <= TLI.getShiftAmountThreshold(ShValTy)) { + SDValue Shift = + DAG.getNode(ISD::SRL, dl, ShValTy, N0.getOperand(0), + DAG.getConstant(ShiftBits, dl, ShiftTy)); + SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, ShValTy); + return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond); + } } } } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE || @@ -3681,7 +3683,8 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, } NewC.lshrInPlace(ShiftBits); if (ShiftBits && NewC.getMinSignedBits() <= 64 && - isLegalICmpImmediate(NewC.getSExtValue())) { + isLegalICmpImmediate(NewC.getSExtValue()) && + ShiftBits <= TLI.getShiftAmountThreshold(ShValTy)) { SDValue Shift = DAG.getNode(ISD::SRL, dl, ShValTy, N0, DAG.getConstant(ShiftBits, dl, ShiftTy)); SDValue CmpRHS = DAG.getConstant(NewC, dl, ShValTy); diff --git a/llvm/test/CodeGen/MSP430/shift-amount-threshold-b.ll b/llvm/test/CodeGen/MSP430/shift-amount-threshold-b.ll index 9022c33b384..98efb30d851 100644 --- a/llvm/test/CodeGen/MSP430/shift-amount-threshold-b.ll +++ b/llvm/test/CodeGen/MSP430/shift-amount-threshold-b.ll @@ -6,14 +6,8 @@ define i16 @testSimplifySetCC_2(i16 %x) { ; CHECK-LABEL: testSimplifySetCC_2: ; CHECK: ; %bb.0: ; %entry -; CHECK-NEXT: clrc -; CHECK-NEXT: rrc r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: cmp #1, r12 +; CHECK-NEXT: and #-64, r12 +; CHECK-NEXT: cmp #64, r12 ; CHECK-NEXT: mov r2, r12 ; CHECK-NEXT: rra r12 ; CHECK-NEXT: and #1, r12 @@ -30,18 +24,9 @@ entry: define i16 @testSimplifySetCC_3(i16 %x) { ; CHECK-LABEL: testSimplifySetCC_3: ; CHECK: ; %bb.0: ; %entry -; CHECK-NEXT: clrc -; CHECK-NEXT: rrc r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: tst r12 -; CHECK-NEXT: mov r2, r13 -; CHECK-NEXT: rra r13 -; CHECK-NEXT: mov #1, r12 -; CHECK-NEXT: bic r13, r12 +; CHECK-NEXT: cmp #64, r12 +; CHECK-NEXT: mov r2, r12 +; CHECK-NEXT: and #1, r12 ; CHECK-NEXT: ret entry: %cmp = icmp ugt i16 %x, 63 @@ -54,17 +39,9 @@ entry: define i16 @testSimplifySetCC_4(i16 %x) { ; CHECK-LABEL: testSimplifySetCC_4: ; CHECK: ; %bb.0: ; %entry -; CHECK-NEXT: clrc -; CHECK-NEXT: rrc r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: tst r12 -; CHECK-NEXT: mov r2, r12 -; CHECK-NEXT: rra r12 -; CHECK-NEXT: and #1, r12 +; CHECK-NEXT: cmp #64, r12 +; CHECK-NEXT: mov #1, r12 +; CHECK-NEXT: bic r2, r12 ; CHECK-NEXT: ret entry: %cmp = icmp ult i16 %x, 64 |
