diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/DSInstructions.td | 23 | ||||
| -rw-r--r-- | llvm/test/MC/AMDGPU/ds.s | 9 |
2 files changed, 28 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td index 7f7aa18c671..41be4c5c1b4 100644 --- a/llvm/lib/Target/AMDGPU/DSInstructions.td +++ b/llvm/lib/Target/AMDGPU/DSInstructions.td @@ -444,17 +444,24 @@ def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">; // DS_GWS_SEMA_RELEASE_ALL // DS_WRAP_RTN_B32 // DS_CNDXCHG32_RTN_B64 -// DS_WRITE_B96 -// DS_WRITE_B128 // DS_CONDXCHG32_RTN_B128 -// DS_READ_B96 -// DS_READ_B128 let SubtargetPredicate = isCIVI in { def DS_WRAP_RTN_F32 : DS_1A1D_RET <"ds_wrap_rtn_f32">, AtomicNoRet<"ds_wrap_f32", 1>; +let mayStore = 0 in { +def DS_READ_B96 : DS_1A_RET<"ds_read_b96", VReg_96>; +def DS_READ_B128: DS_1A_RET<"ds_read_b128", VReg_128>; +} // End mayStore = 0 + +let mayLoad = 0 in { +def DS_WRITE_B96 : DS_1A1D_NORET<"ds_write_b96", VReg_96>; +def DS_WRITE_B128 : DS_1A1D_NORET<"ds_write_b128", VReg_128>; +} // End mayLoad = 0 + + } // let SubtargetPredicate = isCIVI //===----------------------------------------------------------------------===// @@ -745,6 +752,10 @@ def DS_WRITE_SRC2_B64_si : DS_Real_si<0xcd, DS_WRITE_SRC2_B64>; def DS_MIN_SRC2_F64_si : DS_Real_si<0xd2, DS_MIN_SRC2_F64>; def DS_MAX_SRC2_F64_si : DS_Real_si<0xd3, DS_MAX_SRC2_F64>; +def DS_WRITE_B96_si : DS_Real_si<0xde, DS_WRITE_B96>; +def DS_WRITE_B128_si : DS_Real_si<0xdf, DS_WRITE_B128>; +def DS_READ_B96_si : DS_Real_si<0xfe, DS_READ_B96>; +def DS_READ_B128_si : DS_Real_si<0xff, DS_READ_B128>; //===----------------------------------------------------------------------===// // VIInstructions.td @@ -905,3 +916,7 @@ def DS_XOR_SRC2_B64_vi : DS_Real_vi<0xcb, DS_XOR_SRC2_B64>; def DS_WRITE_SRC2_B64_vi : DS_Real_vi<0xcd, DS_WRITE_SRC2_B64>; def DS_MIN_SRC2_F64_vi : DS_Real_vi<0xd2, DS_MIN_SRC2_F64>; def DS_MAX_SRC2_F64_vi : DS_Real_vi<0xd3, DS_MAX_SRC2_F64>; +def DS_WRITE_B96_vi : DS_Real_vi<0xde, DS_WRITE_B96>; +def DS_WRITE_B128_vi : DS_Real_vi<0xdf, DS_WRITE_B128>; +def DS_READ_B96_vi : DS_Real_vi<0xfe, DS_READ_B96>; +def DS_READ_B128_vi : DS_Real_vi<0xff, DS_READ_B128>; diff --git a/llvm/test/MC/AMDGPU/ds.s b/llvm/test/MC/AMDGPU/ds.s index 4b68a823dd2..31f29cc57bb 100644 --- a/llvm/test/MC/AMDGPU/ds.s +++ b/llvm/test/MC/AMDGPU/ds.s @@ -468,3 +468,12 @@ ds_read2st64_b64 v[8:11], v2 // SICI: ds_read2st64_b64 v[8:11], v2 ; encoding: [0x00,0x00,0xe0,0xd9,0x02,0x00,0x00,0x08] // VI: ds_read2st64_b64 v[8:11], v2 ; encoding: [0x00,0x00,0xf0,0xd8,0x02,0x00,0x00,0x08] +ds_read_b128 v[8:11], v2 +// NOSI: error: instruction not supported on this GPU +// CI: ds_read_b128 v[8:11], v2 ; encoding: [0x00,0x00,0xfc,0xdb,0x02,0x00,0x00,0x08] +// VI: ds_read_b128 v[8:11], v2 ; encoding: [0x00,0x00,0xfe,0xd9,0x02,0x00,0x00,0x08] + +ds_write_b128 v2, v[4:7] +// NOSI: error: instruction not supported on this GPU +// CI: ds_write_b128 v2, v[4:7] ; encoding: [0x00,0x00,0x7c,0xdb,0x02,0x04,0x00,0x00] +// VI: ds_write_b128 v2, v[4:7] ; encoding: [0x00,0x00,0xbe,0xd9,0x02,0x04,0x00,0x00] |
