diff options
| -rw-r--r-- | llvm/include/llvm/MCA/Stages/DispatchStage.h | 4 | ||||
| -rw-r--r-- | llvm/lib/MCA/InstrBuilder.cpp | 1 | ||||
| -rw-r--r-- | llvm/lib/MCA/Stages/DispatchStage.cpp | 10 | ||||
| -rw-r--r-- | llvm/tools/llvm-mca/Views/SummaryView.cpp | 3 | ||||
| -rw-r--r-- | llvm/tools/llvm-mca/llvm-mca.cpp | 8 |
5 files changed, 16 insertions, 10 deletions
diff --git a/llvm/include/llvm/MCA/Stages/DispatchStage.h b/llvm/include/llvm/MCA/Stages/DispatchStage.h index e39f03e3263..d80ededeaca 100644 --- a/llvm/include/llvm/MCA/Stages/DispatchStage.h +++ b/llvm/include/llvm/MCA/Stages/DispatchStage.h @@ -68,9 +68,7 @@ class DispatchStage final : public Stage { public: DispatchStage(const MCSubtargetInfo &Subtarget, const MCRegisterInfo &MRI, unsigned MaxDispatchWidth, RetireControlUnit &R, - RegisterFile &F) - : DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth), - CarryOver(0U), CarriedOver(), STI(Subtarget), RCU(R), PRF(F) {} + RegisterFile &F); bool isAvailable(const InstRef &IR) const override; diff --git a/llvm/lib/MCA/InstrBuilder.cpp b/llvm/lib/MCA/InstrBuilder.cpp index e10efb28f77..89904e75cc1 100644 --- a/llvm/lib/MCA/InstrBuilder.cpp +++ b/llvm/lib/MCA/InstrBuilder.cpp @@ -115,6 +115,7 @@ static void initializeUsedResources(InstrDesc &ID, } else { // Remove the leading 1 from the resource group mask. NormalizedMask ^= PowerOf2Floor(NormalizedMask); + UsedResourceGroups |= (A.first ^ NormalizedMask); } for (unsigned J = I + 1; J < E; ++J) { diff --git a/llvm/lib/MCA/Stages/DispatchStage.cpp b/llvm/lib/MCA/Stages/DispatchStage.cpp index ae3d3fd6743..b55ac70307a 100644 --- a/llvm/lib/MCA/Stages/DispatchStage.cpp +++ b/llvm/lib/MCA/Stages/DispatchStage.cpp @@ -25,6 +25,16 @@ namespace llvm { namespace mca { +DispatchStage::DispatchStage(const MCSubtargetInfo &Subtarget, + const MCRegisterInfo &MRI, + unsigned MaxDispatchWidth, RetireControlUnit &R, + RegisterFile &F) + : DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth), + CarryOver(0U), CarriedOver(), STI(Subtarget), RCU(R), PRF(F) { + if (!DispatchWidth) + DispatchWidth = Subtarget.getSchedModel().IssueWidth; +} + void DispatchStage::notifyInstructionDispatched(const InstRef &IR, ArrayRef<unsigned> UsedRegs, unsigned UOps) const { diff --git a/llvm/tools/llvm-mca/Views/SummaryView.cpp b/llvm/tools/llvm-mca/Views/SummaryView.cpp index e3d85507dc8..5aa53b2df90 100644 --- a/llvm/tools/llvm-mca/Views/SummaryView.cpp +++ b/llvm/tools/llvm-mca/Views/SummaryView.cpp @@ -24,7 +24,8 @@ namespace mca { SummaryView::SummaryView(const MCSchedModel &Model, ArrayRef<MCInst> S, unsigned Width, bool EmitBottleneckAnalysis) - : SM(Model), Source(S), DispatchWidth(Width), LastInstructionIdx(0), + : SM(Model), Source(S), DispatchWidth(Width?Width: Model.IssueWidth), + LastInstructionIdx(0), TotalCycles(0), NumMicroOps(0), BPI({0, 0, 0, 0, 0}), ResourcePressureDistribution(Model.getNumProcResourceKinds(), 0), ProcResourceUsage(Model.getNumProcResourceKinds(), 0), diff --git a/llvm/tools/llvm-mca/llvm-mca.cpp b/llvm/tools/llvm-mca/llvm-mca.cpp index 17b19d1818f..ce253af1fe7 100644 --- a/llvm/tools/llvm-mca/llvm-mca.cpp +++ b/llvm/tools/llvm-mca/llvm-mca.cpp @@ -381,17 +381,13 @@ int main(int argc, char **argv) { const MCSchedModel &SM = STI->getSchedModel(); - unsigned Width = SM.IssueWidth; - if (DispatchWidth) - Width = DispatchWidth; - // Create an instruction builder. mca::InstrBuilder IB(*STI, *MCII, *MRI, MCIA.get()); // Create a context to control ownership of the pipeline hardware. mca::Context MCA(*MRI, *STI); - mca::PipelineOptions PO(Width, RegisterFileSize, LoadQueueSize, + mca::PipelineOptions PO(DispatchWidth, RegisterFileSize, LoadQueueSize, StoreQueueSize, AssumeNoAlias, EnableBottleneckAnalysis); @@ -470,7 +466,7 @@ int main(int argc, char **argv) { if (PrintSummaryView) Printer.addView(llvm::make_unique<mca::SummaryView>( - SM, Insts, Width, EnableBottleneckAnalysis)); + SM, Insts, DispatchWidth, EnableBottleneckAnalysis)); if (PrintInstructionInfoView) Printer.addView( |
