diff options
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 27 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/late-pred.ll | 26 |
2 files changed, 49 insertions, 4 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index 66e38cfc8b9..dad314f758e 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -3048,10 +3048,29 @@ bool HexagonInstrInfo::predCanBeUsedAsDotNew(const MachineInstr &MI, return false; } - // Hexagon Programmer's Reference says that decbin, memw_locked, and - // memd_locked cannot be used as .new as well, - // but we don't seem to have these instructions defined. - return MI.getOpcode() != Hexagon::A4_tlbmatch; + // Instruction that produce late predicate cannot be used as sources of + // dot-new. + switch (MI.getOpcode()) { + case Hexagon::A4_addp_c: + case Hexagon::A4_subp_c: + case Hexagon::A4_tlbmatch: + case Hexagon::A5_ACS: + case Hexagon::F2_sfinvsqrta: + case Hexagon::F2_sfrecipa: + case Hexagon::J2_endloop0: + case Hexagon::J2_endloop01: + case Hexagon::J2_ploop1si: + case Hexagon::J2_ploop1sr: + case Hexagon::J2_ploop2si: + case Hexagon::J2_ploop2sr: + case Hexagon::J2_ploop3si: + case Hexagon::J2_ploop3sr: + case Hexagon::S2_cabacdecbin: + case Hexagon::S2_storew_locked: + case Hexagon::S4_stored_locked: + return false; + } + return true; } bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const { diff --git a/llvm/test/CodeGen/Hexagon/late-pred.ll b/llvm/test/CodeGen/Hexagon/late-pred.ll new file mode 100644 index 00000000000..3b690eb97cc --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/late-pred.ll @@ -0,0 +1,26 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +; This generates A4_addp_c, which cannot be used as a dot-new predicate +; producer (resulting in a crash). +; CHECK-NOT: p{{[0-3]+}}.new + +target triple = "hexagon" + +define void @ext4_group_extend() #0 { +entry: + %es.idx.val = load i32, i32* undef, align 4 + %conv1.i = zext i32 %es.idx.val to i64 + %or.i = or i64 undef, %conv1.i + %add20 = add i64 %or.i, undef + %cmp21 = icmp ult i64 %add20, %or.i + br i1 %cmp21, label %if.then23, label %if.end24 + +if.then23: ; preds = %entry + unreachable + +if.end24: ; preds = %entry + unreachable +} + +attributes #0 = { nounwind "target-cpu"="hexagonv65" } + |
